DETAILED ACTION
0Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 19 objected to because of the following informalities: claim 19 recites “the a second mode”. Appropriate correction is required.
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: the prior art of made of record does not teach or fairly suggest the combination of claimed elements “wherein the first power estimator is operable to square the in-phase signal, the second power estimator is operable to square the quadrature signal, and wherein the combiner is operable to, in the first mode, double the output of the active power estimator and, in the second mode, sum the outputs of the first and second power estimators” as recited in independent claim 4.
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: the prior art of made of record does not teach or fairly suggest the combination of claimed elements “wherein the first power estimator is operable to square the in-phase signal, the second power estimator is operable to square the quadrature signal, and wherein the function, in a first mode, doubles the output of the active power estimator and, in the a second mode, sums the outputs of the first and second power estimators” as recited in independent claim 19.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6-8, 10-12, and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Katsube et al. (US 20090310524 A1 in view of Hasegawa (US 20020071507 A1).
Regarding claim 1, apparatus of claim 1 is performed by the apparatus of claim 8. They recite similar limitations. Applicant is kindly advised to refer to rejection of claim 8.
Regarding claim 2, the modified Katsube further teaches the receiver of claim 1, wherein the automatic gain controller is operable to, in a second mode, turn on the inactive power estimator such that both the first and second power estimators are active (Fig. 3, S3 and Par. 78), and control the combiner to generate the estimated signal power using a function of both outputs of the first and second power estimators (Par. 70).
Regarding claim 3, the modified Katsube further teaches the receiver of claim 2, wherein the automatic gain controller is operable to perform energy detection while in the first mode (Fig. 3, S1 and Pars. 46-47).
Regarding claim 6, the modified Katsube further teaches the receiver of claim 1, wherein the automatic gain controller is operable to detect energy of a WLAN frame during the first mode (Fig. 3, S1 and Pars. 46-47, 78) and, in response to detecting the energy, transition to a second mode where the automatic gain controller turns on the inactive power estimator such that both the first and second power estimators are active (Fig. 3, S3 and Pars. 70, 78), and control the combiner to generate the estimated signal power using a function of both outputs of the first and second power estimators (Fig. 3 and Par. 70).
Regarding claim 7, the modified Katsube further teaches the receiver of claim 1, wherein the automatic gain controller is operable to receive an indication of detection of a WLAN frame during the first mode (Fig. 3, S1 and Par. 78 and, in response to detection of the WLAN frame, transition to a second mode where the automatic gain controller turns on the inactive power estimator such that both the first and second power estimators are active (Fig. 3, S3 and Pars. 70, 78), and control the combiner to generate the estimated signal power using a function of both outputs of the first and second power estimators (Fig. 3 and Pars. 70).
Regarding claim 8, Katsube teaches a receiver (Fig. 1), comprising: a radio frequency (RF) front end (Fig. 1, FEM 2); an analog baseband circuit coupled to the RF front end (Fig. 1, 90-degree phase shifter 5); a digital baseband circuit coupled to the analog baseband circuit (Fig. 1); a power estimator comprising a first power estimator operable to receive an in-phase signal (Fig. 1 and Par. 65, I signal processing unit 22 (first power estimator)), a second power estimator operable to receive a quadrature signal (Fig. 1 and Par. 65, Q signal processing unit 23 (second power estimator)), and
an automatic gain controller(Fig. 1 and Par. 73, signal level detection unit 16 performs automatic gain control (AGC) ), the automatic gain controller operable to, in a first mode, turn off one of the first or second power estimators such that the one of the first or second power estimators is an inactive power estimator and the other is an active power estimator (Figs. 1-3 and Pars. 58-60, 78, the first A/D converter is controlled to an active state and the second A/D converter is controlled to a low power consumption state (inactive)), and control the combiner to generate the estimated signal power using a function of an output of active power estimator (Par. 70); where the RF front end and the analog baseband circuit are operable to generate the in-phase signal and the quadrature signal (Fig. 1 and Par. 64, 90-degree phase shifter 5 supplies I local signal and a Q).
Katsube does not expressly disclose a combiner, coupled to outputs of the first and second power estimators, the combiner having an output that supplies estimated signal power; and the automatic gain controller coupled to the output of the combiner However, this feature cannot be considered new or novel in the presence of Hasegawa. Hasegawa teaches baseband signal BS (I (In-phase signal)/Q (Quadrature-phase signal), in practice) is input to the high-speed power calculating circuit 21 and normal power calculating circuit 22 (Fig. 2 and Par. 40) and calculating circuit 23 (combiner) compute the value of the difference of the output from the high-speed power calculating circuit 21 and normal power calculating circuit 22 (Fig. 2) and Par. 48).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the above teaching as taught by Hasegawa into Katsube to perform tracking operation quickly.
Regarding claim 10, the modified Katsube further teaches the receiver of claim 8, wherein the power estimator and the automatic gain controller are part of the digital baseband circuit, and wherein the in-phase signal and the quadrature signal comprise digital signals (Fig. 1).
Regarding claim 11, apparatus of claim 11 is performed by the apparatus of claim 6. They recite similar limitations. Applicant is kindly advised to refer to rejection of claim 6.
Regarding claim 12, the modified Katsube further teaches the receiver of claim 11, wherein the automatic gain controller is operable to perform an automatic gain control algorithm, in the second mode, to control at least one amplifier in at least one of the RF front end, the analog baseband circuit, and the digital baseband circuit (Fig. 1, amplifier 3 and Par. 73).
Regarding claim 15, method of claim 15 is performed by the apparatus of claim 8. They recite similar limitations. Applicant is kindly advised to refer to rejection of claim 8.
Regarding claim 16, method of claim 16 is performed by the apparatus of claim 86. They recite similar limitations. Applicant is kindly advised to refer to rejection of claim 6.
Regarding claim 17, method of claim 17 is performed by the apparatus of claim 87. They recite similar limitations. Applicant is kindly advised to refer to rejection of claim 7.
Regarding claim 18, the modified Katsube further teaches the method of claim 15, further comprising: performing, by the automatic gain controller, an automatic gain control algorithm based on output of the active power estimator (Fig. 3 and Pars. 70-78).
Claims 5, 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Katsube et al. (US 20090310524 A1 in view of Hasegawa (US 20020071507 A1) in further view of Husted et al. (US 20120155347 A1).
Regarding claim 5, the modified Katsube does not explicitly disclose the receiver of claim 1, wherein the automatic gain controller selects the first mode during a listen mode.
However, this feature cannot be considered new or novel in the presence of Husted. Husted teaches a wireless protocol circuitry is placed in the lower power mode while in the listening mode (Pars. 43-44).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the above teaching as taught by Husted into the modified Katsube to lower the power consumption.
Regarding claim 14, apparatus of claim 14 is performed by the apparatus of claim 5. They recite similar limitations. Applicant is kindly advised to refer to rejection of claim 5.
Regarding claim 20, method of claim 20 is performed by the apparatus of claim 5. They recite similar limitations. Applicant is kindly advised to refer to rejection of claim 5.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Katsube et al. (US 20090310524 A1 in view of Hasegawa (US 20020071507 A1) in further view of Butterfield et al. (US 6321075 B1).
Regarding claim 9, the modified Katsube does not explicitly disclose the receiver of claim 8, wherein the power estimator and the automatic gain controller are part of the analog baseband circuit, and wherein the in-phase signal and the quadrature signal comprise analog signals.
However, this feature cannot be considered new or novel in the presence of Butterfield (Fig. 1).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the above teaching as taught by Butterfield into Katsube for performing in the analog domain.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Katsube et al. (US 20090310524 A1 in view of Hasegawa (US 20020071507 A1) in further view of Kubota (US 20100313094 A1).
Regarding claim 13, the modified Katsube further teaches the receiver of claim 11, wherein the automatic gain controller is operable to detect the energy of a portion of a preamble in a WLAN frame (Par. 78),
The modified Katsube does not explicitly disclose the portion having equal average power in both the in-phase and quadrature signals. However, this feature cannot be considered new or novel in the presence of Kubota (Fig. 3 and Pars. 70-74).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the above teaching as taught by Kubota into Katsube to correct errors caused in the receiver.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Arsian et al. US 20190068153 A1 First power detector 15 input to the ACG controller 80 and second power detector 55 input to the ACG controller 80 (Fig. 1)..[line 8 of 0028]…..Note that in other embodiments, power detector 55 may be implemented with only a single threshold for comparison, as described further below. As with the discussion above, when the IF signal level exceeds a given threshold, power detector 55 outputs an active detection signal, IFpkd.sub.1,2, to AGC controller 80. In embodiments, one or more of these active detection signals may be latched signals as described above. In addition, power detector 55 may also provide additional detection signals to AGC controller 80. These detection signals may be active detection signals that are sent from power detector 55 to AGC controller 80 whenever a sample of the IF signal exceeds the high threshold. More specifically, in a receiver such as receiver 1 implemented as a complex receiver, an active detection signal may be sent per sample when the corresponding I or Q sample exceeds the high threshold.
Furuta et al. US 20130100999 A1 analog baseband circuit figure 6
Mori et al. US 20070109170 A1 [0045] The analog I signal is input to the pipelined A/D converter 16, and the analog Q signal is input to the pipelined A/D converter 17, so that the analog I signal and the analog Q signal are converted into a digital I signal and a digital Q signal, respectively. The digital I signal and the digital Q signal which are input to the pipelined A/D converters 16 and 17 to be firstly 6-bit-A/D-converted are output to the power measurement unit 18 as AGC coarse adjustment signals (step 104).
[0050] At first, the AGC fine adjustment symbols 118 are A/D-converted into a 10-bit digital I signal and a 10-bit digital Q signal at the pipelined A/D converters 16 and 17, respectively. The digital I signal and the digital Q signal are output to the digital signal processor 5 connected to the output of the A/D converter 4, and are input to the power measurement unit 18 as AGC fine adjustment signals, respectively. The power measurement unit 18 generates an AGC fine adjustment power obtained by converting the AGC fine adjustment signals into dB (decibel) values and output to the controller 19 (step 107).
Park et al. US 20230246666 A1 Front End, Analog Baseband and Digital Baseband (Fig. 12)
[0191] Each of the first to third unit ADCs 1211, 1212, and 1213 includes an in-phase unit ADC (I_ADC) and an antiphase unit ADC (Q_ADC). Each of the in-phase unit ADCs (I_ADCs) receives the I signal from the RF signal processor and converts the I signal to a digital signal. The antiphase unit ADC (Q_ADC) receives the Q signal from the RF signal processor and converts the Q signal to a digital signal.
0207] The spatial encoder 1230 may output a digital code of “00” based on that a bit of the thermometer code is “000”. In addition, the spatial encoder 1230 may output a digital code of “01” based on that a bit of the thermometer code is “001”, output a digital code of “10” based on that a bit of the thermometer code is “011”, and output a digital code of “11” based on that a bit of the thermometer code is “111”.
Chanca et al. US 8238865 B2 (51) To detect and calibrate for these imperfections, the RF receiver 500 modifies the phase and magnitude of one of the I and Q channel vectors with the gain and phase adjust circuit 524. In one embodiment, as shown in FIG. 10, the Q channel vector is unmodified and the I channel vector is modified in accordance with the coefficients A, B computed by the decoder 540. The variable-gain amplifiers 528 generate .DELTA.I and .DELTA.Q values, and the summer 530 combines them with the original Q channel vector. When the gain and phase adjust circuit 524 is successfully tuned in accordance with the above steps, the resultant post-calibrated vector, I+.DELTA.I+.DELTA.Q, is tuned to coincide with the x-axis (i.e., the ideal I vector), thereby improving the operation of the RF receiver 500.
Konradsson et al. US 11297575 B2 The baseband circuit 106 may be configured to receive, e.g., I and Q (rectangular format) symbols for some embodiments. In some embodiments, the baseband circuit 106 may be configured to receive, e.g., amplitude and phase (polar format) signals. (19) In some embodiments, AGC circuit 108 may be configured to regulate a gain
Chen US 20230291375 A1 [0014] In one embodiment, as shown in FIG. 2F, the first signal 203 is inputted to the power detector 204, wherein the power detector 204 comprises a peak voltage detector 204a and an RMS voltage detector 204b, wherein the peak voltage detector 204a is selected for generating the power level 209 of the power detector 204 when the control signal 207 is in a normal mode, and the RMS voltage detector 204b is selected for generating the power level 209 of the power detector 204 when the control signal 207 is in a fast mode by using a multiplexer 204c.
Myoung et al. US 20180123627 A1 First power detector 114 input to the ACG controller 150 and second power detector 146 input to the ACG controller 150 (Fig. 3A)
Maulik et al. US 20090042526 A1
AGC 330 may also be implemented across the two chips. For example, the components forming the AGC may be broadly categorized into a power detector component 360a and a gain controller component 360b
Ma et al. US 20240072875 A1 FIG. 8 to ensure that the receiving link 10 that has the greatest RSSI is connected to the energy detection unit 2. After the signal of each receiving link 10 passes through the ADC 14, the correlation detection unit 15 performs correlation detection on a packet header. When the SNR and RSSI is small, the energy detection unit 2 performs energy detection on the packet header on the receiving link 10 currently connected to the energy detection unit. AGC adjustment is performed on each receiving link 10 based on results of the correlation detection and the energy detection. The correlation detection unit 15 may be turned off after the correlation is succeeded. Results of energy detection or correlation detection of the plurality of receiving links after the AGC adjustment are integrated.
Gore et al. US 20160241212 A1 [0047] The examples set forth herein relate to a method and apparatus for performing automatic gain control (AGO) in an ultra low power (ULP) wireless receiver. The method includes computing, by an energy detection circuit, a variance in an output signal of an analog-to-digital converter (ADC). The method further includes activating, by the energy detection circuit, an AGC circuit to adjust a gain of at least one component in a radio frequency integrated chip (RFIC) in response to the variance exceeding a threshold. In response to the AGC circuit being activated, the method further includes computing an output power of the output signal, by the AGC circuit, and adjusting the gain of the at least one component
Chen US 20180034428 A1
Dorosenco; et al. US 9553754 B1
Huang et al. US 11271597 B1
Yasumura US 4292598 A
Cadena US 20220377682 A1
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CINDY HUYEN TRANDAI whose telephone number is (571)270-1914. The examiner can normally be reached 8am -4:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wesley L. Kim can be reached at 571-272-7867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Cindy Trandai/Primary Examiner, Art Unit 2648
7/23/2026
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