Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 20-22, 24, 30-32, and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Karatani et al. (United States Patent Application Publication US 2004/0246035), hereinafter Karatani, in view of CHOI (United States Patent Application Publication US 2013/0120043), hereinafter CHOI.
Regarding claim 20, Karatani teaches a system comprising: a first pulse generation circuit operable to generate a first pulse; and a second pulse generation circuit operable to generate a second pulse, wherein: the first pulse generation circuit and the second pulse generation circuit are selectively synchronized ([0049] “The plural clock generating circuits 12a-12e are synchronously controlled by means of the clock synchronous signals outputted from the clock synchronous signal generating circuit 31 so that the clock signals outputted from the clock generating circuits 12a-12e are periodically synchronized.” Plurality of clock generating circuits output or generate clock signals. A clock signal is a series of pulses. Furthermore, the clock signals generated by the plurality of clock generating circuits are synchronized.)
However, Karatani does not explicitly teach when the first pulse generation circuit and the second pulse generation circuit are synchronized, a timing of the first pulse and the second pulse is determined according to a synchronization register.
CHOI teaches when the first pulse generation circuit and the second pulse generation circuit are synchronized, a timing of the first pulse and the second pulse is determined according to a synchronization register ([0060] “The delay control circuit 1120 may include a register controller 1130 and a register 1140. The register controller 1130 may store locking information for a low frequency clock signal in response to the MRS signal. The register controller 1130 may generate register control signals based on the up signal UP and the down signal DN. The register 1140 may generate delay control signals based on the register control signals from the register controller 1130.” [0088] “The phase detector 3100 may compare an external clock signal ECLK and a feedback signal FBCK, and may generate an up signal UP and a down signal DN.” [0089] “The first delay control circuit 3200 and the second delay control circuit 3300 may operate in response to an MRS signal.” Based on the value stored in a register, the clock signal is delayed to synchronized the clock signal with external clock signal. The delay time stored in the register is interpreted as a timing of the first pulse and the second pulse.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Karatani by incorporating the teaching of CHOI of when the first pulse generation circuit and the second pulse generation circuit are synchronized, a timing of the first pulse and the second pulse is determined according to a synchronization register. They are all directed toward controlling a clock signal. As recognized by CHOI, an internal clock signal synchronized with an external clock signal is needed to output the data exactly since the output circuit of the DRAM device needs a clock signal such as a data strobe signal when data is read from the DRAM device ([0006]). By using a timing or a delay of two clock signals stored in a register, since the register is fastest and smallest storge for immediate processing need, the performance can be improved. Therefore, it would be advantageous to incorporate the teaching of CHOI of when the first pulse generation circuit and the second pulse generation circuit are synchronized, a timing of the first pulse and the second pulse is determined according to a synchronization register in order to improve the performance of the system.
Regarding claim 21, Karatani in view of CHOI teaches all the limitations of the system of claim 20, as discussed above.
CHOI further teaches wherein the timing of the first pulse and the second pulse is determined according to a wait time register ([0089] “The first delay control circuit 3200 and the second delay control circuit 3300 may operate in response to an MRS signal.”).
Regarding claim 22, Karatani in view of CHOI teaches all the limitations of the system of claim 20, as discussed above.
CHOI teaches wherein a wait time register is set according to how long it takes signals to propagate to the first pulse generation circuit and/or the second pulse generation circuit (The register 1140 may generate delay control signals based on the register control signals from the register controller 1130.” A delay is based on the error of the clock signal during the propagation of the clock signal. Furthermore, as shown in FIG. 3-5, & 7, the clock signal is also propagating to phase detector, which then signals propagates to delay line that generate the clock signal.).
Regarding claim 24, Karatani in view of CHOI teaches all the limitations of the system of claim 20, as discussed above.
CHOI further teaches wherein the second pulse generation circuit is operable to wait for a number of clock cycles ([0062] “the delay cell 1151 may delay a phase of the external clock signal ECLK by 90° to generate the first clock signal CLKOl. The delay cell 1152 may delay a phase of the first clock signal CLKOl by 90° to generate the second clock signal CLK02. The delay cell 1153 may delay a phase of the second clock signal CLK02 by 90° to generate the third clock signal CLK03. The delay cell 1153 delay a phase of the third clock signal CLK03 by 90° to generate the fourth clock signal CLK04.” Each phase of 90° to delay the signal changes ½ cycle.).
Regarding claim(s) 30-32, and 34, the claim(s) 30-32, and 34 are the method claims of the apparatus claim(s) 20-22, and 24. The claim(s) 30-32, and 34 do not further teach or define the limitation over the limitations recited in the rejected claims above. Therefore, Karatani in view of CHOI teaches all the limitations of the claim(s) 30-32, and 34.
Claim(s) 23 and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Karatani in view of CHOI as applied to claims 20 and 30 above, and further in view of Lee (United States Patent Application Publication US 2005/0226090).
Regarding claim 23, Karatani in view of CHOI teaches all the limitations of the system of claim 20, as discussed above.
However, Karatani in view of CHOI does not teach wherein: the system is operable to change from synchronous to asynchronous in response to a synchronization field of an instruction.
Lee teaches wherein: the system is operable to change from synchronous to asynchronous in response to a synchronization field of an instruction (FIG. 6, [0055] “The synchronous and asynchronous detecting unit 38 comprises a chip selecting signal detecting unit 42, an asynchronous detecting unit 44, a synchronous detecting unit 46 and an asynchronous control signal generating unit 48.” [0056] “The chip selecting signal detecting unit 42 outputs a pulse signal MIXDETPZ for detecting the maximum value tCSmax of the setup time of a chip selecting signal /CS1 to the clock CLK.” [0057] “The asynchronous detecting unit 44 outputs an asynchronous detecting signal MIXDET for detecting the asynchronous setting in response to the pulse signal MIXDETPZ outputted from the chip selecting signal detecting unit 42.” [0083] “Also, the asynchronous set signal MRSASYNC becomes at the high level so that the asynchronous mode is set.” [0084] “FIG. 14 is a timing diagram illustrating the operating of the PSRAM of FIG. 4 when the synchronous mode is changed into the asynchronous mode.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Karatani in view of CHOI by incorporating the teaching of Lee of wherein: the system is operable to change from synchronous to asynchronous in response to a synchronization field of an instruction. As recognized by Lee, various modes such as a synchronous mode, a asynchronous mode or a combined mode can be simultaneously supported to satisfy various specifications required in product market ([0025]). However, since the conventional PSRAM is operated at the asynchronous mode, it cannot be used at the combined mode ([0025]). Thus, by switching between the asynchronous mode and the synchronous mode, the various required specifications can be satisfied. Therefore, it would be advantageous to incorporate the teaching of Lee of wherein: the system is operable to change from synchronous to asynchronous in response to a synchronization field of an instruction in order to satisfy various modes.
Regarding claim(s) 33, the claim(s) 33 is the method claim of the apparatus claim(s) 23. The claim(s) 33 does not further teach or define the limitation over the limitations recited in the rejected claims above. Therefore, Karatani in view of CHOI and further in view of Lee teaches all the limitations of the claim(s) 33.
Claim(s) 25 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Karatani in view of CHOI as applied to claims 20 and 30 above, and further in view of Biederman (United States Patent Application Publication US 2011/0065511), hereinafter Biederman.
Regarding claim 25, Karatani in view of CHOI teaches all the limitations of the system of claim 20, as discussed above.
Karatani teaches the first pulse generation circuit and the second pulse generation circuit ([0049] “The plural clock generating circuits 12a-12e are synchronously controlled by means of the clock synchronous signals outputted from the clock synchronous signal generating circuit 31 so that the clock signals outputted from the clock generating circuits 12a-12e are periodically synchronized.”).
However, Karatani in view of CHOI does not teach wherein the second pulse generation circuit is operable to wait according to an uncertainty in how long it takes signals to propagate to the second generation circuit and/or the first generation circuit.
Biederman teaches wherein the second pulse generation circuit is operable to wait according to an uncertainty in how long it takes signals to propagate to the second generation circuit and/or the first generation circuit ([0027] “At 110, the time of departure values for the messages with respect to the clock of the first device are recorded…At 120, the first device receives a message, referred to herein as a time value transfer message, from the second device. This message comprises time of reception values indicating time of reception of the messages, sent at 110, at the second device, with respect to the clock of the second device.” [0028] “At 130, the first device 20 computes a clock correction value based on the time of reception values (received in the time value transfer message at 120) and the time of departure values (recorded at 110). The clock correction value represents a time and/or frequency offset between the clock of the first device and the clock of the second device. At 140, the first device 20 sends the clock correction value to the second device 30.” Since the clock error occurs during the propagation of signals between them, Biederman suggests that the error of the clock is interpreted as an uncertainty in how long it takes to propagate to the second pulse generation circuit and/or the first pulse generation circuit.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Karatani in view of CHOI by incorporating the teaching of Biederman of wherein the second pulse generation circuit is operable to wait according to an uncertainty in how long it takes signals to propagate to the second generation circuit and/or the first generation circuit. As recognized by Biederman, the clock of a second device may become out of sync or offset with respect to a clock of a first device that communicates to each other ([0020]). By correcting the out of synchronized clocks, which takes account the error due to the uncertainty of propagation between two devices, the clocks of two devices that communicates to each other can be synchronized. Therefore, it would be advantageous to incorporate the teaching of Biederman of wherein the second pulse generation circuit is operable to wait according to an uncertainty in how long it takes signals to propagate to the second generation circuit and/or the first generation circuit.
Regarding claim(s) 35, the claim(s) 35 is the method claim of the apparatus claim(s) 25. The claim(s) 35 does not further teach or define the limitation over the limitations recited in the rejected claims above. Therefore, Karatani in view of CHOI and further in view of Biederman teaches all the limitations of the claim(s) 35.
Claim(s) 26-28 and 36-38 are rejected under 35 U.S.C. 103 as being unpatentable over Karatani in view of CHOI as applied to claims 20 and 33 above, and further in view of Kollmitzer et al. (United States Patent US 10606794), hereinafter Kollmitzer.
Regarding claim 26, Karatani in view of CHOI teaches all the limitations of the system of claim 20, as discussed above.
However, Karatani in view of CHOI does not teach wherein the first pulse generation circuit is operable to wait for a next on-grid clock cycle before triggering a change of a state of synchronization.
Kollmitzer teaches wherein the first pulse generation circuit is operable to wait for a next on-grid clock cycle before triggering a change of a state of synchronization (FIG. 1B “110 Slave devices clock signal from master device” “120 Timeout monitor detects pulses of clock signal and or timeouts associated with the pulses” “130 If a timeout event is detected, timeout monitor resets slave shift register to synchronize with master shift register” FIG. 7 “730 Determine whether a timeout threshold expires before a second pulse is detected or whether a second pulse is detected before the timeout threshold is determined to be expired” Until second pulse is detected, the synchronization is waited and not reset.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Karatani in view of CHOI by incorporating the teaching of Kollmitzer of wherein the first pulse generation circuit is operable to wait for a next on-grid clock cycle before triggering a change of a state of synchronization. They are all directed toward synchronizing clock signals. As recognized by Kollmitzer, since master device has unidirectional control over one or more slave devices via a bus, if a device on the bus becomes unsynchronized with the clock signal for the bus, means to resynchronize that the device must exist to enable proper communication device, which may be different depending on the type of communication protocol used on the bus (“Background” [Col 2. Lines 19-24]). By waiting until the second pulse is received to reset the synchronization with the master device, the faulty detection of synchronization can be prevented. Therefore, it would be advantageous to incorporate the teaching of Kollmitzer of wherein the first pulse generation circuit is operable to wait for a next on-grid clock cycle before triggering a change of a state of synchronization in order to avoid faulty detection of synchronization.
Regarding claim 27, Karatani in view of CHOI teaches all the limitations of the system of claim 20, as discussed above.
Kollmitzer further teaches wherein the first pulse generation circuit is operable to wait N clock cycles before triggering a change of state of synchronization (FIG. 1B “110 Slave devices clock signal from master device” “120 Timeout monitor detects pulses of clock signal and or timeouts associated with the pulses” “130 If a timeout event is detected, timeout monitor resets slave shift register to synchronize with master shift register” FIG. 7 “720 Detect a first pulse of the clock signal” “730 Determine whether a timeout threshold expires before a second pulse is detected or whether a second pulse is detected before the timeout threshold is determined to be expired” [Col. 2 Lines 54-57] “the timeout may correspond to a timeout threshold (e.g., a threshold length of a time period) expiring without detecting a subsequent pulse (or clock cycle) of the clock signal after an initial pulse is detected.”).
Regarding claim 28, Karatani in view of CHOI teaches all the limitations of the system of claim 20, as discussed above.
Kollmitzer further teaches wherein the system comprises a synchronization management circuit that is in a first state for 1 out of every N clock cycles and is not in the first state for N-1 of every N clock cycles (FIG. 1B “110 Slave devices clock signal from master device” “120 Timeout monitor detects pulses of clock signal and or timeouts associated with the pulses” “130 If a timeout event is detected, timeout monitor resets slave shift register to synchronize with master shift register” FIG. 7 “730 Determine whether a timeout threshold expires before a second pulse is detected or whether a second pulse is detected before the timeout threshold is determined to be expired” [Col. 2 Lines 54-57] “the timeout may correspond to a timeout threshold (e.g., a threshold length of a time period) expiring without detecting a subsequent pulse (or clock cycle) of the clock signal after an initial pulse is detected.” FIG. 1B “Slave Shift Register” A state that the first clock cycle that detects a pulse is the first cycle of number of cycles, which is the timeout threshold. During the timeout threshold with N number of cycles, the state that does not detect the subsequent pulse is interpreted as not in the first state for N-1 of every N clock cycles.).
Regarding claim(s) 36-38, the claim(s) 36-38 are the method claims of the apparatus claim(s) 26-28. The claim(s) 36-38 do not further teach or define the limitation over the limitations recited in the rejected claims above. Therefore, Karatani in view of CHOI and further in view of Kollmitzer teaches all the limitations of the claim(s) 36-38.
Allowable Subject Matter
Claims 29 and 39 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Karatani teaches synchronizing a plurality of clock generation circuits. However, Karatani does not teach “wherein a value of N is based on a value stored in a grid-step register of the synchronization management circuit.”
CHOI teaches a register and a register controller to control delay of clock signal. However, CHOI does not teach “wherein a value of N is based on a value stored in a grid-step register of the synchronization management circuit.”
Kollmitzer teaches detect a first pulse of the clock signal from a master device in a slave device. Kollmitzer further teaches that when the timeout threshold expires before a second pulse is detected, reset the shift register to synchronize the shift register with a master shift register of the master device. However, Kollmitzer does not teach does not teach “wherein a value of N is based on a value stored in a grid-step register of the synchronization management circuit.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bishop et al. (United States Patent Application Publication US 2019/0156236) teaches reduction and/or mitigation of crosstalk in quantum bit gates.
Sivan et al. (United States Patent Application Publication US 2023/0261763) teaches that a latency of a communication channel between quantum controller module is deterministic and controllable according to a system clock domain.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HYUN SOO KIM whose telephone number is (571)270-1768. The examiner can normally be reached Monday - Friday 8:30 am - 5:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at (571)270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/HYUN SOO KIM/Examiner, Art Unit 2176