Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 8 is objected to because of the following informalities:
In claim 8, lines 3 and 5, in each line “the power transistor” should read as -- the first power transistor--, respectively.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 10; 15, 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by SATO (US 20180342992 A1), hereafter referred to as "SATO".
Regarding claims 1 and 10, in the embodiment of Figs. 1-4, SATO discloses:
A power amplifier (Figs. 1-4, power amplifier circuit 100) comprising:
a first power transistor (transistor Q1) configured to amplify a first input Radio Frequency (RF) signal (RFIN), and output a first output RF signal (RFOUT1);
a first bias circuit (bias circuits 110) configured to operate in a first communication mode the first communication mode is a 2G communication mode (paragraph [0016] lines 7-10, power amplifier circuit 100 amplifies power of a signal of a communication standard such as, for example, a second-generation mobile communication system (2G) per claim 10), and comprising a first transistor (Fig. 2, transistor Qc) configured to supply a first bias current (bias current Ibias1) to the first power transistor (via base of the transistor Q1, as shown in Figs. 2-4); and
a second bias circuit (bias circuit 120) configured to operate in a second communication mode wherein the second communication mode is a 4G communication mode or a 5G communication mode (paragraph [0016] lines 7-13, The power amplifier circuit 100 amplifies power of a signal of a communication standard such as, for example, a fourth-generation mobile communication system (4G), a fifth-generation mobile communication system (5G) per claim 10), and comprising a second transistor (transistor Qd) configured to supply a second bias current (bias current Ibias2) to the first power transistor (via base of the transistor Q1, as shown in Figs. 2-4).
Regarding claims 15 and 20, in the embodiment of Fig. 5, SATO discloses:
A power amplifier (Fig. 5, power amplifier circuit 100C, note: bias circuit 120 is only shown in the first stage, but the configuration in the first stage for transistor Q1is not limited to that the first stage and may be used in the second stage for transistor Q2 per paragraph [0057]) comprising:
a first power transistor (transistor Q1) configured to amplify a first input Radio Frequency (RF) signal (input signal RFin), and output a first output RF signal (amplification signal RFout1);
a first transistor (transistor Qc of bias circuit 110A) configured to operate in a first communication mode and a second communication mode (paragraph [0016] lines 7-13, The power amplifier circuit 100 amplifies power of a signal of a communication standard such as, for example, a second-generation mobile communication system (2G), a fourth-generation mobile communication system (4G), a fifth-generation mobile communication system (5G)), and comprising a first terminal wherein the first terminal of the first transistor is an emitter of the first transistor (Qc emitter, per claim 20) configured to supply a first bias current (Ibias1) to the first power transistor (via base of Q1, as shown in Fig. 5);
a second power transistor (transistor Q2) configured to amplify a second input RF signal (RFout1 as an input to Q2 base via element C4) corresponding to the first output RF signal, and output a second output RF signal (amplification signal RFout2);
a second transistor (Fig. 5, transistor Qc of bias circuit 130A, note: Bias Circuit 120-120B of Figs. 1-3 will be used as an example of how the configuration of power amplifier circuit 100-100B of Figs. 1-3 may be used per paragraph [0057]) configured to operate in the first communication mode (paragraph [0016] lines 7-10, power amplifier circuit 100 amplifies power of a signal of a communication standard such as, for example, a second-generation mobile communication system (2G)) and comprising a first terminal wherein the first terminal of the second transistor is an emitter of the second transistor (Fig. 5, Qc emitter (analogously Qc of 110A of fig. 2), per claim 20) configured to supply a second bias current (Fig. 5, bias current Ibias3) to the second power transistor (via base of Q2, as shown in Fig. 5); and
a third transistor (Figs. 1-3, transistor Qd of bias circuit 120-12B) configured to operate in the second communication mode (paragraph [0040] lines 1-10, in the bias circuit 120B, the resistance of the variable resistor Radj may be changed according to at least one of the communication standard (e.g. 2G, 3G, 4G, etc.)) and comprising a first terminal wherein the first terminal of the third transistor is an emitter of the third transistor (Qc emitter, per claim 20) configured to supply a third bias current (Fig. 1-3, Ibias2) to the second power transistor (Figs. 1-3, shown to be connected to base of Q1 as analogous to Q2 in Fig. 5).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-9, 11-14, and 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over SATO (US 20180342992 A1) in view of NI (cited by the applicant), hereafter referred to as “SATO” and “NI”, respectively.
Regarding claims 2-9, 11-14, 16-19 in the embodiment of Figs. 1-5, SATO discloses:
a first and second input RF signal wherein each RF signal is input in a terminal (Fig. 5, RFin, and output of transistor Q1 input to element C4), and a first, second, and third bias circuit (Fig. 5, bias circuits 110A, 120B, and 130A) comprising a first, second, and third transistor (Fig. 5, transistor Qc, and transistors Qd of bias circuits 110A, 120B, and 130A) wherein first, second, and third transistor each comprises a first terminal wherein each first terminal of each transistor is an emitter of the first, second, and third transistors (Fig. 5, emitters of transistor Qc and transistors Qd of 110A, 120B, and 130A), and wherein the first and second transistors are configured to supply the first and second bias current to the first power transistor (Figs. 2 and 5, Qc and Qd are shown to supply transistor Q1 with Ibias1 and Ibias2) and the third bias circuit is configured to supply the third bias current to the second power transistor (Fig. 5, Qc of 130A supplies Ibias3 to transistor Q2), wherein the first input RF signal corresponds to the second output RF signal (Fig. 5, RFout1 terminal input to element C4, corresponds to RFout2, note: bias circuit 120 is only shown in the first stage, but the configuration in the first stage for transistor Q1is not limited to that the first stage and may be used in the second stage for transistor Q2 per paragraph [0057], and therefore, the configuration of the first and second stage can be switched), and a first and second communication mode (paragraph [0016] lines 7-13, The power amplifier circuit 100 amplifies power of a signal of a communication standard such as, for example, a second-generation mobile communication system (2G), a fourth-generation mobile communication system (4G), a fifth-generation mobile communication system (5G)).
However, Sato is silent in teaching a first, second, and third linearization circuit comprising a first and a second capacitor, and a capacitor of the third linearization circuit (“third” capacitor per claim 17), respectively, comprising a first and second terminal connected in series with a first and a second resistor, and a resistor of the third linearization circuit (“third” resistor per claim 17), respectively, connected to the second terminals of each capacitor, respectively, and each linearization circuit is connected between the terminal to which the first and second input RF signal is input and the first terminal of the first, second, and third transistor, respectively, wherein each linearization circuit is configured to couple a portion of the first and second input RF signal to an output of the first terminal of the first, second, and third transistor, respectively.
NI teaches:
a linearization circuit (Fig. 3 and 6B, linearizing circuit 104) comprising a capacitor comprising a first and second terminal and a resistor connected in series between the terminal of the RF signal input, the second terminal of the capacitor and the first terminal of the transistor (Fig. 6B, linearizing circuit 104 shows resistor R6 and capacitor C6 is connected in series between input (IN) and emitter of transistor Qb between nodes 110 and 114 along path 112), wherein each linearization circuit is configured to couple a portion of the input RF signal and the first terminal of the transistor (per paragraph [0052], linearizing circuit 104 along the path 112 couples the nodes 110 and 114).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention for emitter of the transistors of each bias circuit taught by SATO (Fig. 5 and similarly taught in NI Fig. 2) to further include a linearization circuit taught by NI (Fig. 3 and 6B) to yield rectification on the base-emitter junction to thereby correct AM-AM distortion (NI, paragraph [0048] lines 5-11), thereby suggesting the obviousness of such a combination. It would be further obvious to one having ordinary skill in art for the resistors to be connected to one shared capacitor in the linearization circuit as it is known in the art to compensate for two capacitors in parallel add capacitance directly, as known in the art, thereby suggesting the obviousness of such a modification.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALANE LIENG whose telephone number is (571)272-5739. The examiner can normally be reached Monday-Friday 6:30 - 4:00 CST.
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/Malane Lieng/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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