Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Allowable Subject Matter
Claim 14, 15, 19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 5, 6, 11, 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yan et al. (US 20160300947 A1) hereafter referred to as Yan. Lu et al. (US 20240014319 A1) hereafter referred to as Lu is evidence for claim 12.
In regard to claim 1 Yan teaches a [“FIG. 2a-2f schematically illustrate in cross-sectional views a method of forming a semiconductor device”] semiconductor device, comprising:
a semiconductor substrate [“semiconductor substrate 210 may be a base semiconductor substrate of an SOI substrate”]; and
a first transistor [see Fig. 2f “although the gate structures 230a, 230b are only depicted in a very schematic way, no limitation of the present disclosure is intended”] disposed on the semiconductor substrate,
wherein the first transistor includes:
an insulation structure [“insulating materials 215a, 215b”] disposed on the semiconductor substrate;
a channel region [“the semiconductor film 216a, 216b may be provided by a semiconductor material, e.g., silicon or silicon germanium” “completely remove a portion of the semiconductor film 216a below the gate structure 230a, leaving portion 217a (FIG. 2d), and to completely remove a portion of the semiconductor film 216b below the gate structure 230b, leaving portion 217b (FIG. 2d)”] disposed on the insulation structure and including a first semiconductor layer, wherein the channel region [see Fig. 2f the channel is only the portion of 217a and 217b under the gate “the gate structures 230a, 230b may comprise one or more gate dielectric material layers, e.g., ...”] extends in a direction crossing the semiconductor substrate;
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first source [see the sources include 243a and the part of 217a under 243a, similarly include 243b and the part of 217b under 243b] and drain [see 242a, 242b] regions electrically connected to the channel region;
a first gate insulating layer [“the gate structures 230a, 230b may comprise one or more gate dielectric material layers, e.g., one or more high-k material layers, a work function adjusting material, a gate electrode and an optional gate cap in accordance with gate first techniques. Alternatively, the gate ...”] disposed on the channel region; and
a first gate electrode [see above “a gate electrode”] disposed on the first gate insulating layer,
wherein a first region [i.e. the sources include 243a and the part of 217a under 243a, similarly include 243b and the part of 217b under 243b, see “the semiconductor film 216a, 216b may be provided by a semiconductor material, e.g., silicon or silicon germanium” and “the process P4 may comprise an epitaxial growth process for growing epitaxially grown material, also referred to as epi material, at both sides of each gate structure 230a, 230b to fill each of the trenches 240a, 240b with epi material and growing epi material on an upper surface of the semiconductor film 217a at the opposing side of the gate structure 230a. In accordance with some illustrative embodiments of the present disclosure, the epi material grown in the process P4 may be doped with dopants for forming source/drain regions. In accordance with some illustrative examples herein, the epi material may comprise SiGe material or SiC material”] that is one of the first source and drain regions and a second region [i.e. the drains “the process P4 may comprise an epitaxial growth process for growing epitaxially grown material, also referred to as epi material, at both sides of each gate structure 230a, 230b to fill each of the trenches 240a, 240b with epi material and growing epi material on an upper surface of the semiconductor film 217a at the opposing side of the gate structure 230a. In accordance with some illustrative embodiments of the present disclosure, the epi material grown in the process P4 may be doped with dopants for forming source/drain regions. In accordance with some illustrative examples herein, the epi material may comprise SiGe material or SiC material”] that is another one of the first source and drain regions include different materials [see the sources can have a combination of Si/SiGe or Si/SiC or SiGe/SiC whereas the drain can only be SiGe or SiC, thus they are different materials and the claim limitation is satisfied] or have different crystal structures.
In regard to claim 4 Yan teaches wherein the first region is disposed on [see Fig. 2f the 243 and 217 are on 215] the insulation structure, wherein the second region is disposed on [see Fig. 2f the 242 touches 210, for the sake of clarity, the Examiner notes that “on” does not require touching, however see Fig. 2f the 242 touches 210 ] or at one surface of the semiconductor substrate, and wherein a first side of the channel region [see Fig. 2f the channel is only the portion of 217a and 217b under the gate “the gate structures 230a, 230b may comprise one or more gate dielectric material layers, e.g.,” see that 217 on the left of channel is part of the source] is connected to the first region, and a second side of the channel region that is opposite to the first side of the channel region is connected to [see Fig. 2f see the right side of channel is touching 242] the one surface of the semiconductor substrate or the second region.
In regard to claim 5 Yan teaches wherein a thickness of the channel region or a thickness of the first region is less [see Fig. 2f the thickness of the channel is the thickness of 217 however see that the thickness of 242 also includes the thickness of 215] than a thickness of the second region.
In regard to claim 6 Yan teaches wherein the channel region includes a portion [see Fig. 2f the channel is surrounded on top by the gate insulating layer and below by the 215 thus satisfying “at least partially” ] at least partially surrounded by the insulation structure and the first gate insulating layer.
In regard to claim 11 Yan teaches wherein the channel region is connected to [see Fig. 2e, Fig. 2f “in general, a trench 240a with varying depth may be formed, for example, even extending deep into the base semiconductor portions 212a, 212b” “the epi material grown in the process P4 may be doped with dopants for forming source/drain regions” see Fig. 2f the channel is electrically connected to the substrate by 242 which is the drain and conducts electricity] a bulk region of the semiconductor substrate.
In regard to claim 12 Yan teaches further comprising: a second transistor [“The person skilled in the art will appreciate that semiconductor devices may be fabricated as P-channel MOS transistors or PMOS transistors and N-channel transistors or NMOS transistors; both types of transistors may be fabricated with or without mobility-enhancing stressor features or strain-inducing features. It is noted that a circuit designer can mix and match device types, using PMOS and NMOS devices, stressed and unstressed, to take advantage of the best characteristics of each device type as they best suit the semiconductor device under design”] having an operating voltage less [see Yan see “the semiconductor film 216a, 216b may be provided by a semiconductor material, e.g., silicon or silicon germanium” and “the process P4 may comprise an epitaxial growth process for growing epitaxially grown material, also referred to as epi material, at both sides of each gate structure 230a, 230b to fill each of the trenches 240a, 240b with epi material and growing epi material on an upper surface of the semiconductor film 217a at the opposing side of the gate structure 230a. In accordance with some illustrative embodiments of the present disclosure, the epi material grown in the process P4 may be doped with dopants for forming source/drain regions. In accordance with some illustrative examples herein, the epi material may comprise SiGe material or SiC material”, see the sources can have a combination of Si/SiGe or Si/SiC or SiGe/SiC whereas the drain can only be SiGe or SiC, thus each combination is a different structure and will inherently have different operating voltage] than an operating voltage of the first transistor and having a structure different from a structure of the first transistor.
Lu is evidence of inherent effect of lattice mismatch “the grown material (such as Si) of the first step could be different from the grown material (such as, SiGe, SiC, W, or other selective grown material) of the second step in order to reduce the resistances of Source/Drain regions or increase the stress force to the initial portions of Source/Drain regions into the channel region to increase mobility”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yan in view of Hutin et al. (US 20170162672 A1) hereafter referred to as Hutin
In regard to claim 2 Yan teaches wherein the first region includes a second semiconductor layer [i.e. the sources include 243a and the part of 217a under 243a, similarly include 243b and the part of 217b under 243b, see “the semiconductor film 216a, 216b may be provided by a semiconductor material, e.g., silicon or silicon germanium” and “the process P4 may comprise an epitaxial growth process for growing epitaxially grown material, also referred to as epi material, at both sides of each gate structure 230a, 230b to fill each of the trenches 240a, 240b with epi material and growing epi material on an upper surface of the semiconductor film 217a at the opposing side of the gate structure 230a. In accordance with some illustrative embodiments of the present disclosure, the epi material grown in the process P4 may be doped with dopants for forming source/drain regions. In accordance with some illustrative examples herein, the epi material may comprise SiGe material or SiC material”] and wherein the second region includes a partial portion [see Fig. 2e, Fig. 2f “in general, a trench 240a with varying depth may be formed, for example, even extending deep into the base semiconductor portions 212a, 212b” “the epi material grown in the process P4 may be doped with dopants for forming source/drain regions” the channel is electrically connected to the substrate by 242 which is the drain and conducts electricity] of the semiconductor substrate but does not state having a conductivity type opposite to a conductive type of the channel region.
However this has to do with threshold voltage, see Yan “It is important to note that the characteristic voltage level at which the conductivity state changes (usually called the “threshold voltage”) therefore characterizes the switching behavior of the MOSFET” “PDSOI and FDSOI devices differ by the thickness of a silicon layer which is disposed over a buried oxide layer” “Furthermore, FDSOI devices do not require any doping in the channel region. In general, drawbacks of bulk semiconductor devices, like threshold roll-off, higher sub-threshold slope body effects, short channel effects, etc., are reduced”.
See Hutin “The channel 134 extends between the source 161 and the drain 162. For a transistor 1 of FDSOI type, the portion 133 of the channel 134 exhibits a level of doping that is typically lower than 5*10.sup.15 cm.sup.−3, and typically of the order of 10.sup.15 cm.sup.−3. The thickness of the channel 134 is, for example, between 5 and 15 nm”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Yan to include having a conductivity type opposite to a conductive type of the channel region.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that it is difficult to avoid any doping altogether, thus a low level of opposite doping is useful to set threshold voltage.
In regard to claim 3 Yan and Hutin as combined teaches wherein the first semiconductor layer and the second semiconductor layer are connected [see Yan Fig. 2f] to each other.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yan in view of Yamagata (JP 2003151985 A)
In regard to claim 7 Yan does not teach wherein the channel region or the first gate electrode is inclined or vertical to a first surface or a second surface of the semiconductor substrate.
See Yan teaches using SOI substrate.
See Yamagata teaches how to do this using bulk substrate, see Fig. 3 see “LOCOS (Local Oxidation of Silicon) method is used to form the element isolation film 5 made of, for example, a silicon oxide film” “silicon nitride film is subjected to pattern etching by photolithography to form an oxidation resistant mask layer having an opening in a portion where the element isolation film 5 is formed. After that, steam oxidation at 1000 to 1050 ° C. is performed to form the element isolation layer 5 having a thickness of 300 to 800 nm, for example” “heat treatment is performed at 800 to 900 ° C. to densify the silicon oxide film 8” “using the epitaxial technique, SiGe is non-selectively formed in at least the SiGe HBT forming region” “if necessary, the silicon germanium mixed crystal layer 9 (9A, 9A B, 9C) is doped with an impurity so that a desired portion thereof has a boron concentration of 5 × 10 .sup.18 to 3 × 10 .sup.19 cm .sup.−3 , for example”.
If the method of Yamagata is applied to Yan, then the device of Yan can be grown even on bulk substrate, and see that the “isolation layer 5” is equivalent of “insulating materials 215a, 215b” of Yan, and see that at the edge of the “isolation layer 5” under the channel and the gate there is a slope down in “isolation layer 5” and after that is the drain.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Yan to include wherein the channel region or the first gate electrode is inclined or vertical to a first surface or a second surface of the semiconductor substrate.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to be able to make the devices of Yan even using bulk substrate for flexibility of design and manufacture and also to save money by using bulk substrate.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yan in view of Cai et al. (US 20090114971 A1) hereafter referred to as Cai
In regard to claim 8 Yan teaches wherein the first transistor is one of a pair [see Fig. 2f] of first transistors adjacent to each other in one direction,
but does not teach wherein the second region is shared by the pair of first transistors, and wherein the pair of first transistors has a symmetrical structure in the one direction with respect to the second region.
See Cai Figs. 1A-1D see Fig. 1D has two pFET “The pFET 31, which is formed adjacent to the left isolation oxide region 35L, is composed of an p+ doped source region 32(S), an n doped channel region CH1 and the left half of a shared, p+ doped region 37. The pFET 33 is composed of the right hand half of the shared, p+ doped region 37, an n doped channel region CH2 and a p+ drain region 36 formed between the pFET 31 and the right isolation oxide region 35R” see Cai teaches CMOS inverter in Fig. 1B, the Examiner notes that a person of ordinary skill in the art is aware of other logic gates such as OR, AND, NAND and NOR.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Yan to include wherein the second region is shared by the pair of first transistors, and wherein the pair of first transistors has a symmetrical structure in the one direction with respect to the second region.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to save space by sharing drains.
Claim(s) 9, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yan in view of Yan et al. (CN 108461545 A) hereafter referred to as Yan-45
In regard to claim 9 Yan teaches further comprising: a first contact connected to the first region [see contacts see Fig. 2F “Subsequent to the formation of the raised source 243a, 243b and the drain region 242a, 242b, source/drain contacts (indicated by a dotted broken line in FIG. 2f) may be formed”] and a second contact connected to the second region,
but does not state wherein the second region includes a low concentration region and a high concentration region having a doping concentration higher than a doping concentration of the low concentration region, and wherein the second contact is connected to the high concentration region.
However this is common practice, see Fig. 2E see “gate electrode 50” “p-type well 32” “FIG. 2C and FIG. 2E, the first metal layer 100 disposed on the source a bottom electrode opening 70, the first metal layer 100 can be made of silicide (Silicides), nickel, titanium, aluminum or combinations thereof” “the first metal layer 100 and a part of the n-type heavily doped region 33 and part of the p-type heavily doped contact region 34, and to form an ohmic contact”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Yan to include wherein the second region includes a low concentration region and a high concentration region having a doping concentration higher than a doping concentration of the low concentration region, and wherein the second contact is connected to the high concentration region.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is using a higher concentration is good to make good electrical contact.
In regard to claim 10 Yan teaches wherein the channel region is connected to [see combination, the higher concentration region is to make good electrical contact] the low concentration region.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yan in view of Joshi et al. (US 20070235806 A1) hereafter referred to as Joshi
In regard to claim 13 Yan teaches wherein the second transistor [see claim 12 Yan teaches 3 combinations see the sources can have a combination of Si/SiGe or Si/SiC or SiGe/SiC whereas the drain can only be SiGe or SiC, and the structure is the same as in Fig. 2f] includes a second gate insulating layer disposed on the semiconductor substrate, a second gate electrode disposed on the second gate insulating layer, and second source and drain regions disposed at both sides of the second gate electrode, respectively, and wherein the second source and drain regions each include [see Fig. 2e, Fig. 2f “in general, a trench 240a with varying depth may be formed, for example, even extending deep into the base semiconductor portions 212a, 212b” “the epi material grown in the process P4 may be doped with dopants for forming source/drain regions” the channel is electrically connected to the substrate by 242 which is the drain and conducts electricity] a partial portion of the semiconductor substrate.
See Joshi teaches using much more variety of devices than Yan, see “Especially for complex chips and arrays with a large number of devices, device leakage (both gate and subthreshold) chip leakage power can be overwhelming, for PD-SOI and FD-SOI IC chips. When multiplied by the millions and even billions of devices on a state of the art IC, even 100 picoAmps (100 pA) of leakage in each of a million circuits, for example, results in chip leakage on the order of 100 milliAmps (100 mA). Thus, as chip features have shrunk, these leakage sources have become more prominent, especially for PD-SOI and FD-SOI IC chips. Approaches to increasing device V.sub.T to mitigate subthreshold leakage, e.g., with thicker gate dielectric or back biasing device channels for example, have been applied uniformly across all circuits on a PD-SOI and FD-SOI IC chip. Moreover, chip performance could be optimized while minimizing chip power, by allowing mixed circuits of different device types, i.e., PD-SOI, FD-SOI and bulk, rather than being constrained to using a single technology device for all circuits”, see “Further, for a particular device, subthreshold current increases exponentially with the magnitude of the device's drain to source voltage (V.sub.ds) and reduces exponentially with the magnitude of the device's V.sub.T. This is especially true in what is known as partially depleted (PD) or fully depleted (FD) silicon on insulator (SOI) technologies, where devices are formed in a thin uniform silicon surface layer. PD-SOI and FD-SOI FETs have suffered from dramatically increased subthreshold leakage to the point that, in some PD-SOI and FD-SOI IC chips it is the leakage dominant source”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Yan to include wherein the second transistor includes a second gate insulating layer disposed on the semiconductor substrate, a second gate electrode disposed on the second gate insulating layer, and second source and drain regions disposed at both sides of the second gate electrode, respectively, and wherein the second source and drain regions each include a partial portion of the semiconductor substrate.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to have the design ability to include lower voltage bulk devices with both source and drain in the substrate as a means of controlling leakage.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yan
In regard to claim 16 Yan teaches a first contact connected [“Subsequent to the formation of the raised source 243a, 243b and the drain region 242a, 242b, source/drain contacts (indicated by a dotted broken line in FIG. 2f) may be formed”] to the first region and a second contact connected to the second region are disposed at a second position
but does not show the wherein a gate contact connected to the first gate electrode is disposed at a first position in one direction, and the “different from the first position in the one direction”.
See “the gate structures 230a, 230b may comprise one or more gate dielectric material layers, e.g., one or more high-k material layers, a work function adjusting material, a gate electrode and an optional gate cap in accordance with gate first techniques” “the gate structure 130 (formed by a gate dielectric 132, a gate electrode 134, a gate contact 136 and sidewall spacers 138) disposed over the semiconductor substrate 110 of the SOI type can now very tightly control the full volume of the body of the semiconductor device 100”.
See in Yan Fig. 2f the source contact is on source, drain contact is on drain and gate contact is on gate i.e. in different positions going left to right in Fig. 2f.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Yan to include wherein a gate contact connected to the first gate electrode is disposed at a first position in one direction, and the “different from the first position in the one direction”.
The motivation is to make contact to operate the device.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yan
In regard to claim 17 Yan teaches further comprising: a circuit region including [“The person skilled in the art will appreciate that semiconductor devices may be fabricated as P-channel MOS transistors or PMOS transistors and N-channel transistors or NMOS transistors; both types of transistors may be fabricated with or without mobility-enhancing stressor features or strain-inducing features. It is noted that a circuit designer can mix and match device types, using PMOS and NMOS devices, stressed and unstressed, to take advantage of the best characteristics of each device type as they best suit the semiconductor device under design”] the semiconductor substrate and the first transistor;
but does not teach and a cell region disposed on the circuit region and including a memory cell structure.
However this is common usage of transistors, see Yan “In modern electronic equipment, integrated circuits (ICs) experience a vast applicability in a continuously spreading range of applications” “Generally, in applying a voltage exceeding a characteristic voltage level to the gate electrode, the conductivity state of the channel is changed and switching between a conducting state or “ON-state” and a non-conducting state or “OFF-state” may be achieved”.
see Parat see Fig. 1 “Each memory cell 120a-n of the string 121 can be coupled in series with and can be between a select gate (e.g., a drain select gate) 111 adjacent to (e.g., in contact with) the conductive channel 110 and a select gate (e.g., a source select gate) 112 adjacent to (e.g., in contact with) the conductive channel 110” “Referring to FIG. 7, a schematic block diagram of an exemplary solid-state device 480 is illustrated. The solid-state device 480 can be, for example, a non-volatile memory device, such as a solid state memory device (e.g., a memory device such as a three-dimensional NAND memory device). The solid-state device 480 can include a printed circuit board (PCB) 481 and a flash memory component 400 as disclosed herein operably coupled to the PCB 481. The solid-state device 480 can also include a memory controller 482 operably coupled to the PCB 481. In addition, the solid-state device 480 can include a data buffer 483 operably coupled to the PCB 481” “select gates 111 and 112 can each include a gate dielectric 113 adjacent to (e.g., in contact with) conductive channel 110 and a control gate 114 adjacent to (e.g., in contact with) a corresponding gate dielectric 113”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Yan to include and a cell region disposed on the circuit region and including a memory cell structure.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to use transistors of Yan in chips including memory cells to perform work such as for example memory operations to save and read data in memory.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yan et al. (US 20160300947 A1) hereafter referred to as Yan in view of Yamagata (JP 2003151985 A)
In regard to claim 18 Yan teaches a [“FIG. 2a-2f schematically illustrate in cross-sectional views a method of forming a semiconductor device”] semiconductor device, comprising:
a semiconductor substrate [“semiconductor substrate 210 may be a base semiconductor substrate of an SOI substrate”]; and
a plurality of transistors [“The present disclosure relates to a method of forming a semiconductor device and to semiconductor devices, wherein the semiconductor devices are integrated on or in a chip”] disposed on the semiconductor substrate and including [“The person skilled in the art will appreciate that semiconductor devices may be fabricated as P-channel MOS transistors or PMOS transistors and N-channel transistors or NMOS transistors; both types of transistors may be fabricated with or without mobility-enhancing stressor features or strain-inducing features. It is noted that a circuit designer can mix and match device types, using PMOS and NMOS devices, stressed and unstressed, to take advantage of the best characteristics of each device type as they best suit the semiconductor device under design”] a first transistor and a second transistor having different structures;
wherein the first transistor [see Fig. 2f] includes:
an insulation structure [“insulating materials 215a, 215b”] disposed on the semiconductor substrate;
a channel region [“the semiconductor film 216a, 216b may be provided by a semiconductor material, e.g., silicon or silicon germanium” “completely remove a portion of the semiconductor film 216a below the gate structure 230a, leaving portion 217a (FIG. 2d), and to completely remove a portion of the semiconductor film 216b below the gate structure 230b, leaving portion 217b (FIG. 2d)”] disposed on the insulation structure and including a first semiconductor layer;
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source [see the sources include 243a and the part of 217a under 243a, similarly include 243b and the part of 217b under 243b] and drain [see 242a, 242b] regions electrically connected to the channel region;
a gate insulating layer [“the gate structures 230a, 230b may comprise one or more gate dielectric material layers, e.g., one or more high-k material layers, a work function adjusting material, a gate electrode and an optional gate cap in accordance with gate first techniques. Alternatively, the gate ...”] disposed on the channel region; and
a gate electrode [see above “a gate electrode”] disposed on the gate insulating layer,
wherein one of the source and drain regions includes a partial portion [see Fig. 2e, Fig. 2f “in general, a trench 240a with varying depth may be formed, for example, even extending deep into the base semiconductor portions 212a, 212b” “the epi material grown in the process P4 may be doped with dopants for forming source/drain regions” the channel is electrically connected to the substrate by 242 which is the drain and conducts electricity] of the semiconductor substrate,
but does not teach wherein the channel region extends in a direction inclined or vertical to the semiconductor substrate.
See Yan teaches using SOI substrate.
See Yamagata teaches how to do this using bulk substrate, see Fig. 3 see “LOCOS (Local Oxidation of Silicon) method is used to form the element isolation film 5 made of, for example, a silicon oxide film” “silicon nitride film is subjected to pattern etching by photolithography to form an oxidation resistant mask layer having an opening in a portion where the element isolation film 5 is formed. After that, steam oxidation at 1000 to 1050 ° C. is performed to form the element isolation layer 5 having a thickness of 300 to 800 nm, for example” “heat treatment is performed at 800 to 900 ° C. to densify the silicon oxide film 8” “using the epitaxial technique, SiGe is non-selectively formed in at least the SiGe HBT forming region” “if necessary, the silicon germanium mixed crystal layer 9 (9A, 9A B, 9C) is doped with an impurity so that a desired portion thereof has a boron concentration of 5 × 10 .sup.18 to 3 × 10 .sup.19 cm .sup.−3 , for example”.
If the method of Yamagata is applied to Yan, then the device of Yan can be grown even on bulk substrate, and see that the “isolation layer 5” is equivalent of “insulating materials 215a, 215b” of Yan, and see that at the edge of the “isolation layer 5” under the channel and the gate there is a slope down in “isolation layer 5” and after that is the drain.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Yan to include wherein the channel region extends in a direction inclined or vertical to the semiconductor substrate.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to be able to make the devices of Yan even using bulk substrate for flexibility of design and manufacture and also to save money by using bulk substrate.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yan et al. (US 20160300947 A1) hereafter referred to as Yan in view of Parat et al. (US 20190043875 A1) hereafter referred to as Parat
In regard to claim 20 Yan teaches a [“FIG. 2a-2f schematically illustrate in cross-sectional views a method of forming a semiconductor device” “The present disclosure relates to a method of forming a semiconductor device and to semiconductor devices, wherein the semiconductor devices are integrated on or in a chip”] an electronic system, comprising:
a semiconductor device [“FIG. 2a schematically illustrates, in a cross-sectional view, a semiconductor device structure 200 formed in and over a semiconductor substrate 210”]; and
wherein the semiconductor device comprises a semiconductor substrate [“semiconductor substrate 210 may be a base semiconductor substrate of an SOI substrate”], and a first transistor [see Fig. 2f “although the gate structures 230a, 230b are only depicted in a very schematic way, no limitation of the present disclosure is intended”] disposed on the semiconductor substrate,
wherein the first transistor includes:
an insulation structure [“insulating materials 215a, 215b”] disposed on the semiconductor substrate;
a channel region [“the semiconductor film 216a, 216b may be provided by a semiconductor material, e.g., silicon or silicon germanium” “completely remove a portion of the semiconductor film 216a below the gate structure 230a, leaving portion 217a (FIG. 2d), and to completely remove a portion of the semiconductor film 216b below the gate structure 230b, leaving portion 217b (FIG. 2d)”] disposed on the insulation structure and including a first semiconductor layer, wherein the channel region [see Fig. 2f the channel is only the portion of 217a and 217b under the gate “the gate structures 230a, 230b may comprise one or more gate dielectric material layers, e.g., ...”] extends in a direction crossing the semiconductor substrate;
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source [see the sources include 243a and the part of 217a under 243a, similarly include 243b and the part of 217b under 243b] and drain [see 242a, 242b] regions electrically connected to the channel region;
a gate insulating layer [“the gate structures 230a, 230b may comprise one or more gate dielectric material layers, e.g., one or more high-k material layers, a work function adjusting material, a gate electrode and an optional gate cap in accordance with gate first techniques. Alternatively, the gate ...”] disposed on the channel region; and
a gate electrode [see above “a gate electrode”] disposed on the gate insulating layer,
wherein a first region [i.e. the sources include 243a and the part of 217a under 243a, similarly include 243b and the part of 217b under 243b, see “the semiconductor film 216a, 216b may be provided by a semiconductor material, e.g., silicon or silicon germanium” and “the process P4 may comprise an epitaxial growth process for growing epitaxially grown material, also referred to as epi material, at both sides of each gate structure 230a, 230b to fill each of the trenches 240a, 240b with epi material and growing epi material on an upper surface of the semiconductor film 217a at the opposing side of the gate structure 230a. In accordance with some illustrative embodiments of the present disclosure, the epi material grown in the process P4 may be doped with dopants for forming source/drain regions. In accordance with some illustrative examples herein, the epi material may comprise SiGe material or SiC material”] that is one of the source and drain regions and a second region [i.e. the drains “the process P4 may comprise an epitaxial growth process for growing epitaxially grown material, also referred to as epi material, at both sides of each gate structure 230a, 230b to fill each of the trenches 240a, 240b with epi material and growing epi material on an upper surface of the semiconductor film 217a at the opposing side of the gate structure 230a. In accordance with some illustrative embodiments of the present disclosure, the epi material grown in the process P4 may be doped with dopants for forming source/drain regions. In accordance with some illustrative examples herein, the epi material may comprise SiGe material or SiC material”] that is another one of the source and drain regions include different materials [see the sources can have a combination of Si/SiGe or Si/SiC or SiGe/SiC whereas the drain can only be SiGe or SiC, thus they are different materials and the claim limitation is satisfied] or have different crystal structures
but does not state a main substrate; the semiconductor device disposed on the main substrate; a controller electrically connected to the semiconductor device on the main substrate.
However this is common usage of transistors, see Yan “In modern electronic equipment, integrated circuits (ICs) experience a vast applicability in a continuously spreading range of applications” “Generally, in applying a voltage exceeding a characteristic voltage level to the gate electrode, the conductivity state of the channel is changed and switching between a conducting state or “ON-state” and a non-conducting state or “OFF-state” may be achieved”.
see Parat see Fig. 1 “Each memory cell 120a-n of the string 121 can be coupled in series with and can be between a select gate (e.g., a drain select gate) 111 adjacent to (e.g., in contact with) the conductive channel 110 and a select gate (e.g., a source select gate) 112 adjacent to (e.g., in contact with) the conductive channel 110”
“Referring to FIG. 7, a schematic block diagram of an exemplary solid-state device 480 is illustrated. The solid-state device 480 can be, for example, a non-volatile memory device, such as a solid state memory device (e.g., a memory device such as a three-dimensional NAND memory device). The solid-state device 480 can include a printed circuit board (PCB) 481 and a flash memory component 400 as disclosed herein operably coupled to the PCB 481. The solid-state device 480 can also include a memory controller 482 operably coupled to the PCB 481. In addition, the solid-state device 480 can include a data buffer 483 operably coupled to the PCB 481” “select gates 111 and 112 can each include a gate dielectric 113 adjacent to (e.g., in contact with) conductive channel 110 and a control gate 114 adjacent to (e.g., in contact with) a corresponding gate dielectric 113”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Yan to include a main substrate; the semiconductor device disposed on the main substrate; a controller electrically connected to the semiconductor device on the main substrate.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to use transistors of Yan in chips which are connected to other circuits on the chip and also to circuits on other chips, all connected together by a circuit board to perform work such as for example memory operations to save and read data in memory.
Conclusion
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893
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