DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on June 17, 2024
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 20, 2024 is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR INTEGRATE CIRCUIT DEVICE COMPRISING WITH IMPROVED GATE CONTACT PLACEMENT
Election/Restrictions
Applicant’s election of Species I (Figs. 1-15B, claims 1-6) in the reply filed on September 10, 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "their gates" in line 5. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “a gate of the first transistor being mutually connected to a gate of the second transistor”
Claim 1 recites the limitation "their drains" in line 5. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “a drain of the first transistor mutually connected to a drain of the second transistor”
Claim 1 recites the limitation "their gates" in line 7. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “a gate of the third transistor being mutually connected to a gate of the fourth transistor”
Claim 1 recites the limitation "their drains" in line 7. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “a drain of the third transistor mutually connected to a drain of the fourth transistor”
Claim 1, lines: 18-19 recite the limitation “the second and fourth transistors share a source, and the source is connected to a second power supply…” It is unclear if “a source” is a new source or is the same source defined in lines: 16-17. For purposes of examination this will be interpreted as “ the second and fourth transistors share a second source, and the second source is connected to a second power supply…”
Allowable Subject Matter
Claims 1-6 would be allowed if rewritten to overcome the 112 rejections above.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Ino (US 2009/0046085), Sessions (US Pat. No. 6,198,306), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 1 (from which claims 2-6 depend), the first gate contact is placed at a position overlapping the third transistor in planar view.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ino (US 2009/0046085) discloses (Fig. 5B) a CMOS buffer device with a double cascaded design, first transistor PT1, second transistor NT1, gates of PT1 and NT1 connected at NDI, and drains of PT1 and NT1 connected at ND1, third transistor PT2, fourth transistor NT2, gates of PT2 and NT2 connected at ND1, drains of PT2 and NT2 connected at ND2, sources of NT1 and NT2 connected at source supply VSS2 and sources of PT1 and PT2 connected at power supply VDD2. Ino does not disclose the first gate contact is placed at a position overlapping the third transistor in planar view.
Sessions (US Pat. No. 6,198,306) discloses (Fig. 4) a CMOS buffer device with first transistor 17, second transistor 18, gates of the first and second transistors connected at an input 10 and drains of the first and second transistors connected to line 16, third transistor 21 and fourth transistor 22, in which gates of the third and fourth transistors are connected together at unlabeled node. Sessions does not disclose the first gate contact is placed at a position overlapping the third transistor in planar view.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm.
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/GUSTAVO G RAMALLO/Examiner, Art Unit 2812
