DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/25/2025 has been entered. Claims 1-10 and 12-20 are currently pending in the application. An action follows below:
Response to Arguments
The priority objection and the rejection of claim 8 under 35 USC 112(a) in the previous Office action 08/28/2025 have been withdrawn in light of the amendment to the claims.
In response to the rejections under 35 U.S.C. 102 and 103 in the previous Office action, Applicant has amended independent claim 1 to include new limitation and provided on pages 7-8 of the amendment argument, which has been fully considered and is persuasive. Therefore, the rejections have been withdrawn. However, see the below new ground(s) of rejections necessitated by the current amendment.
Notice to Applicant(s)
Examiner notes that the specification is not the measure of invention. Therefore, limitations contained therein can’t be read into the claims for the purpose of avoiding the prior art. See In re Sporck, 55 CCPA 743, 386 F.2d 924, 155 USPQ 687 (1968).
Further, the names/ terms of the features/elements used in the pending application or pending claims may be different from the names/terms of the matching features/ elements of the prior arts; however, the matching features/ elements of the prior arts contain all characteristics/ functions of the features/elements DEFINED by the pending claims.
Note that in order to avoid confusion, the below citations in the below rejection(s) are mere one or more places in the reference to disclose the "claimed" limitation(s) and/or are directed to one or more of embodiments disclosed by the cited reference(s). In other words, the “claimed” features/limitations may be read in other places in the reference or other embodiments of the reference. In order to better understand how the claimed limitations are taught by the reference(s), a review of the entire reference(s) is suggested by the examiner. Applicant is reminded a prior art reference must be considered in its entirety, i.e., as a whole, including portions that would lead away from the claimed invention as not all relevant paragraphs may have been cited in the rejection. W.L. Gore & Associates, Inc. v. Garlock, Inc., 721 F.2d 1540, 220 USPQ 303 (Fed. Cir. 1983), cert. denied, 469 U.S. 851 (1984).
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9, 10, 12, 13 and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Bang et al. (US 2020/0091252 A1; hereinafter Bang) in view of Tian et al. (US 2021/0176903 A1; hereinafter Tian.)
As per claim 1, Bang discloses a display apparatus [1] (see at least Fig. 1) comprising:
a flexible substrate [SUB] (Fig. 4) formed of a material having flexibility (see at least ¶ 65) and including an active area [DA], an inactive area [NDA] disposed around the active area (Fig. 4,) the active area [DA] including an anode electrode [AE], a light-emitting layer [EML], and a cathode electrode [CE] (see at least Fig. 12/15/16,) and the inactive area [NDA] including an emission driver and a scan driver (see at least Figs. 4 and 12/15/16; ¶ 75, disclosing the circuit GDC comprising the driving circuits for generating and outputting scan signals [as one or more scan driver] and the driving circuits for generating and outputting light emission control signals [as one or more emission driver],)
a thin film transistor [T6] in the active area and including a semiconductor layer, a gate electrode, and a source electrode and a drain electrode (see at least Fig. 12/15/16; ¶¶ 102, 112;)
a planarization layer disposed on the thin film transistor (see at least Fig. 12/15/16, disclosing a planarization layer comprising the element 30 and/or the element 40 and disposed on the thin film transistor T6,) wherein the anode electrode is disposed over the planarization layer (see at least Fig. 12/15/16;)
a bank layer [PDL] disposed on the anode electrode [AE] (see at least Fig. 12/15/16;)
a connection pattern [E-CNT] located at the inactive area [NDA], disposed on the planarization layer and including a plurality of first holes [H_VIA1] (see at least Fig. 12/15/16,) wherein the cathode electrode [CE] extends to the inactive area [NDA] and contacts the connection pattern [E-CNT] (see at least Fig. 12/15/16;)
a low voltage supply line [E-VSS] electrically connected to the connection pattern [E-CNT] in the inactive area [NDA] (see at least Fig. 12/15/16;) and
a dam structure [DM1, DM2] disposed on a part of the low voltage supply line [E-VSS] (see at least Fig. 12/15/16.)
an encapsulation layer [TFE] disposed on the cathode electrode [CE] (see at least Fig. 12/15/16;)
a touch insulating layer [TS-IL1] disposed on the encapsulation layer [TFE] (see at least Fig. 7;)
a touch sensing unit [TS] disposed above the encapsulation layer [TFE] in the active area [DA] (see at least Fig. 12/15/16,) the touch sensing unit including a connection portion [CP1] disposed on the encapsulation layer [TFE] (see at least Fig. 7, disclosing a first conductive layer TS-CL1 disposed on the encapsulation layer [TFE]; Fig. 9; ¶¶ 147-148, disclosing the first conductive layer TS-CL1 including the connection portion [CP1]) and a plurality of touch electrodes [SP1 and/or SP2] (see at least Figs. 7, 8, 10, 11; ¶ 150, disclosing the touch sensing unit TS including touch electrodes [SP1, SP2] in the second conductive layer TS-CL2 which is on the touch insulating layer [TS-IL1], as shown in Fig. 7;) ,
wherein the touch insulating layer [TS-IL1] is disposed between the connection portion [CP1] and the plurality of touch electrodes [SP1/ SP2] (see at least Fig. 7, disclosing the touch insulating layer [TS-IL1] disposed between the first conductive layer TS-CL1 [[the first conductive layer TS-CL1 including the connection portion CP1, as discussed above or see at least Fig. 9; ¶¶ 147-148]] and the second conductive layer TS-CL2 [[the second conductive layer TS-CL2 including the plurality of touch electrodes [SP1/ SP2], as discussed above or see at least Fig. 10; ¶ 150]],) and
wherein the plurality of first holes of the connection pattern overlap with the cathode electrode (see at least Fig. 15, disclosing 4 first holes [H_VIA1] of the connection pattern [E-CNT] overlapping with the cathode electrode CE_1; also see Fig. 13 showing 4 of first holes [H_VIA1] of the connection pattern [E-CNT] overlapping with the cathode electrode CE_C.)
Accordingly, Bang discloses all limitations of this claim except for “a ground line disposed in the inactive area and formed in a same layer as the plurality of touch electrodes,” as claimed.
However, in the same field of endeavor, Tian discloses a related display device (see at least ¶ 1) comprising a touch sensing unit [100] including a plurality of touch electrodes [40 and/or 50], and a ground line [30] disposed in the inactive area and formed in a same layer as the plurality of touch electrodes (see at least Fig. 4; ¶ 42,) thereby simplifying the manufacturing process of the touch sensing unit/substrate without increasing the cost of material and equipment (see at least ¶ 42) and discharging the static charges on the touch sensing unit/substrate in a faster and more significant manner (see at least ¶ 56.) Thus, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of invention of the pending application to modify the display apparatus of Bang to include a ground line, in view of the teaching in the Tian reference, to improve the above modified display apparatus of the Bang reference for the predictable result of simplifying the manufacturing process of the touch sensing unit/substrate without increasing the cost of material and equipment and discharging the static charges on the touch sensing unit/substrate in a faster and more significant manner. Accordingly, the display device of Bang in view of Tian obvious renders all limitations of this claim.
As per claim 2, Bang discloses the connection pattern and the anode electrode formed on a same layer (see at least Fig. 12/15/16; ¶ 171, disclosing the connection pattern E-CNT and the anode electrode AE formed on a same layer 40 and formed of the same material layer.)
As per claim 3, Bang discloses the low voltage supply line and the source electrode and drain electrode formed on a same layer (see at least Fig. 12/15/16, disclosing the low voltage supply line E-VSS, the source electrode, and drain electrode of the TFT T6 formed on a same layer 20 and formed of the same material layer.)
As per claim 4, Bang discloses the plurality of first holes [H_VIA1] spaced apart from one another (see at least Fig. 12/14/15/16/17.)
As per claim 5, Bang discloses the dam structure formed by the planarization layer and the bank layer (see at least Fig. 12/15/16.)
As per claim 6, Bang discloses at least a portion of the connection pattern disposed between the planarization layer and the bank layer (see at least Fig. 12/15/16.)
As per claim 7, Bang discloses the low voltage supply line [E-VSS] disposed between the substrate [SUB] and the dam structure (see at least Fig. 12/15/16.)
As per claim 9, Bang discloses the connection pattern [E-CNT] contacting a top and side surfaces of the planarization layer [40] (see at least Fig. 12/15/16.)
As per claim 10, Bang discloses wherein the touch sensing unit further includes a plurality of touch routing lines [SL1/SL2] disposed in the inactive area [NDA] (see at least Fig. 8, 10.)
As per claim 12, Bang discloses: wherein the connection portion is in contact with the encapsulation layer (see at least Figs. 7-9; ¶¶ 143, 148, disclosing the touch sensing unit comprising the first conductive layer TS-CL1 including a connection portion CP1, disposed on the encapsulation layer TFE, and being in direct contact with the encapsulation layer TFE.)
As per claim 13, Bang discloses two plurality of touch electrodes [SP1] connected to the connection portion [CP1] through contact holes of the touch insulating layer [TS-TL1] (see at least Figs. 8, 9; ¶¶ 140, 149, 150.)
As per claim 15, Bang discloses the display apparatus further comprising a shielding layer [SHL/SHL-1/SHL-2] disposed between the connection pattern [E-CNT] and the emission driver [in the GDC; see the discussion in the rejection of claim 1; or see ¶ 75] in the inactive area [NDA] (see at least Fig. 12/15/16,) wherein the shielding layer [SHL/SHL-1/SHL-2] is electrically connected to the low potential power line [E-VSS] (see at least Fig. 12/15/16.)
As per claim 16, Bang discloses the connection pattern [E-CNT] having a mesh structure surrounding the plurality of first holes [H_VIA1] and the shielding layer having a single-layer structure overlapping the plurality of first holes and the mesh structure (see at least Figs. 12, 14, 15-17.)
As per claim 17, Bang discloses a first end of the shielding layer [SHL/SHL-1/SHL-2] overlapping the emission driver and a second end of the shielding layer contacting the low potential power line [E_VSS] (see at least Fig. 12/15/16.)
As per claim 18, Bang discloses the planarization layer [30, 40] including a first planarization layer [30] disposed on the thin film transistor [T6] and a second planarization layer [40] disposed on the first planarization layer [30] (see at least Fig. 12/15/16,) wherein the shielding layer [SHL/SHL-1/SHL-2] is disposed between the first planarization layer and the second planarization layer (see at least Fig. 12/15/16,) and the connection pattern [E-CNT] is disposed on the second planarization layer (see at least Fig. 12/15/16.)
As per claim 19, Bang discloses the display apparatus further comprising a passivation layer [30] disposed between the planarization layer [40] and the emission driver [of GDC] (see at least Fig. 12/15/16,) wherein the shielding layer [SHL/SHL-1/SHL-2] is electrically connected to the low potential power line [E-VSS] through a first connection hole in the passivation layer (see at least Fig. 12/15/16.)
As per claim 20, Bang discloses the connection pattern [E-CNT] being in contact with the passivation layer through a second connection hole in the planarization layer, wherein the second connection hole is spaced away from the first connection hole (see at least Fig. 12/15/16.)
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Bang in view of Tian, as applied to claim 10, and further in view of Lee et al. (US 2018/0032189 A1; hereinafter Lee.)
As per claim 14, Bang discloses the plurality of touch routing lines overlap the one or more of the emission driver see at least Figs. 4, 8, 10, 12/15/16, disclosing the plurality of touch routing lines SL2 overlapping the GDC circuit including one or more of the emission driver; see the rejection of claim 1 or see ¶ 75.) Accordingly, Bang discloses all limitations of this claim except for a plurality of emission clock lines, as claimed.
However, in the same field of endeavor, Lee discloses a related display device (DD; see at least Fig. 1) comprising: a scan driving circuit [GDC] including an emission driver [EC-C] and a scan driver; a plurality of emission clock lines [CL1, CL2] disposed in the non-active area; and a plurality of scan clock lines [CL3, CL4] disposed in the non-active area (see at least Figs. 5A, 5B, disclosing a GDC including a plurality of GDS, each GDS including an emission stage/driver [EC-C] and a gate driving stage/scan driver [GC-C]; further see at least Figs. 11A, 12A, 13A, 14A, disclosing the GDC, a plurality of emission clock lines [CL1, CL2], and a plurality of scan clock lines [CL3, CL4] disposed in the non-active area [NDA];) a connection pattern disposed above the emission driver and the plurality of emission clock lines in the non-active area (see at least Figs. 11A, 12A, 13A, 14A, disclosing a connection pattern [at least part of EP-L2/ EP-L2b of the conductive portion EP-5/ EP-6/ EP-7/ EP-8] disposed above the emission driver [ED-C in GDC] and the plurality of emission clock lines [CL1, CL2] in the non-active area [NDA];) and a shielding layer [EP-L1/ EP-L1a/ EP-L1b/ EP-L1c] disposed between the connection pattern [EP-L2/ EP-L2b] and one or more of the emission driver [ED-C in GDC] and the plurality of emission clock lines [CL1, CL2] in the non-active area [NDA], the shielding layer [EP-L1/ EP-L1a/ EP-L1b/ EP-L1c] electrically connected to the low potential power line [E-VSS] (see at least Figs. 11A, 12A, 13A, 14A.)
Bang, as discussed above, discloses the scan driving circuit [GDC] comprising the scan driver for generating and outputting the scanning signals and the emission driver for generating and outputting the light emission control signals, but is silent to a plurality of emission clock lines and a plurality of scan clock lines all disposed in the non-active area. Lee remedies for the deficiency of Bang by explicitly disclosing the above-discussed plurality of emission clock lines required for the emission driver generating and outputting the light emission control signals and the above-discussed plurality of scan clock lines required for the scan driver generating and outputting the scanning signals (see Lee at least Fig. 5B.) Thus, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of invention of the pending application to recognize Lee remedying the deficiency of Bang, by explicitly disclosing the plurality of emission clock lines and the plurality of scan clock lines, as respectively required by the emission driver and the scan driver or to modify the display device of Bang to include the plurality of emission clock lines and the plurality of scan clock lines, in view of the teaching in the Lee reference, in order to allow the emission driver generating and outputting the light emission control signals and the scan driver generating and outputting the light emission control signals to operate the display device.
Accordingly, the display device of Bang in view of Tian and Lee obvious renders all limitations of this claim.
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the claimed invention is directed to a display device capable of securing a design margin of a cathode electrode by separately disposing a shielding layer capable of preventing a driving signal noise, increasing an accuracy of touch sensing, and improving touch sensitivity. Claim 8 identifies the uniquely distinct limitations, “wherein the connection pattern and the cathode electrode are in contact with each other within a contact hole formed in the inactive area, the contact hole penetrating through the planarization layer and the bank layer.” The closest prior arts, discussed above, either singularly or in combination, fail to anticipate or render the above underlined limitations in combination with all of the other claimed limitations particularly recited by this claim.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jimmy H Nguyen whose telephone number is (571) 272-7675. The examiner can normally be reached on Monday-Friday 8:30AM-6PM.
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/Jimmy H Nguyen/
Primary Examiner, Art Unit 2626