DETAILED ACTION
This action is in response to the remarks and amendments filed on August 4th, 2026. Claims 1-20 are pending and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed August 4th, 2026 have been fully considered but they are not persuasive.
Applicant argues on page 9 of “Remarks” that “First, Keenan’s KGD [known good die] is a reference for a single integrated circuit, not a ‘multi-device substrate comprising one or more regions, each region of the one or more regions have a plurality of devices formed thereon,’ as the claims require. Keenan at 742. Keenan’s sole disclosure of a KGD is that “[a]n error-free image, or a reconstructed image obtained from an IC built with a known-good-die (KGD), is used as the reference” for defect detection. Id. This describe using an image of a single known-good IC as a baseline for comparison. This is not a canonical design that maps device locations across multiple regions of a multi-device substrate.” Examiner respectfully disagrees. Keenan’s KGD is directed towards a single integrated circuit. However, this single integrated circuit contains multiple devices such as transistors, diodes, a microprocessor, circuits, and joints. (Keenan Section 2.2 “This provides a direct line of access (through the silicon) to the ICs transistors, since all wires and metallization are near the top of the IC.”; Section 3.2 “The influence from noise is mitigated and the image is classified into groups represented by objects on the IC, such as circuits, joints, and board background.”) (Wafer World “Although the diodes, transistors, and microprocessors that make up an integrated circuit have specific functions, they seamlessly work together to perform multiple tasks and calculations.”) The single integrated circuit of Keenan therefore does contain multiple devices of different device types. Furthermore, the KGD of Keenan represents a die which is known to be free of defects and align with the desired specifications of the desired die. Therefore, the KGD of Keenan meets the broadest reasonable interpretation of a golden die, as it represents the desired locations of devices in the integrated circuit design.
Applicant argues on page 9 of “Remarks” that “Second, Keenan's KGD does not "indicat[e] a location of each device in each region of the one or more regions," as the claims recite. There is no disclosure in Keenan of using a reference die to identify where different devices are located across regions of a substrate. Rather, Keenan's comparison-based approach simply detects structural changes within a single IC by comparing it to a defect-free baseline image. Id. at 741-42.” Examiner respectfully disagrees. The KGD of Keenan represents a desired outcome from construct of a die. The core purpose of a KGD is to ensure that dies that are produced and compared to the KGD contain the same devices in the same locations with the same function (This is further supported by the disclosure of Bertin Section 4.1 “A Known Good Die (KGD) is defined as ‘a package type fully supported by suppliers to meet or exceed quality, reliability, and functional data sheet specifications, with non-standardized (die specific) but completely and electronically transferable mechanical specifications’.”). The KGD must include the locations of the devices to ensure that the die which is being compared has the same design and functionality as the KGD, and that the die which is being compared to meets the functional data sheet specifications. Therefore, the KGD does include at least the location of each device within each region.
Applicant argues on pages 9-10 of “Remarks” that “Third, because Keenan's KGD is limited to a single-IC context, Keenan does not teach "mapping locations of the identified defects to corresponding locations on the golden die" in the context of a multi-device substrate with multiple regions. Keenan therefore does not teach or suggest "identifying a golden die corresponding to the multi-device substrate, the golden die representing a canonical design of devices formed on the multi-device substrate and indicating a location of each device in each region of the one or more regions;" "analyzing the image to identify defects in the image of the multi-device substrate by comparing the image of the multi-device substrate to the golden die;" or "mapping locations of the identified defects to corresponding locations on the golden die," as recited in claim 1.” Examiner respectfully disagrees. As shown with reference to the above arguments, the KGD of Keenan is analogous to the golden die of the current disclosure, as they both represent the desired design of a die which can be used for comparison to identify manufacturing defects. The difference image (Keenan Figure 6) between the KGD and the test die show the detected defects (Keenan Figure 7) in the locations in which they appear on the test die, and also show the location of the corresponding component on the KGD image.
Applicant argues on page 10 of “Remarks” that “Furthermore, a POSITA would not have been motivated to modify Said to utilize a reference (i.e., a known-good-die) to detect defects on its dies. Said teaches away from the proposed combination because Said specifically discloses that it its defect detection method is a "reference-free approach that is based on analyzing a set of significant features to filter out suspect artifacts leaving only the desired defects." Said at p. 132 (emphasis added). Said discloses that such a technique is cheaper and easier to maintain and that it would "automatically inspect each unit for defects providing for efficient baseline characterization and rapid excursion detection." Id. at Abstract. Moreover, Said describes other systems (e.g., reference-based systems) as "expensive, require[ing] a lot of resources to sustain, and [] dependent on manual tuning and review for unit's inspection." Id. at p. 130. ” Examiner respectfully disagrees. The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). The disclosure of Keenan would suggest to a person of ordinary skill in the art that a KGD reference based approach for defect detection is possible with its own pros and cons and could be used in conjunction with the disclosure of Said. For at least the reasons stated above, the 35 U.S.C. 103 rejections of claims 1-20 are maintained.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over “Die Level Defects Detection in Semiconductor Units” (herein after referred to by its primary author, Said) in view of “INTEGRATED CIRCUIT FAILURE DETECTION USING IR LASER” (herein after referred to by its primary author, Keenan).
In regards to claim 1, Said teaches an inspection system, comprising: an inspection device configured to capture one or more images of a multi-device substrate (Said Section II “Each tray/carrier gets its image captured by a single pass under the line-scan camera as shown in Fig. 1.” Examiner note: The input image shown in figure 1 contains multiple die, each die is analogous to a device), the multi-device substrate comprising one or more regions, each region of the one or more regions having a plurality of devices Said Figure 1); and a computing system in communication with the inspection device, the computing system configured to identify defects on the multi-device substrate by performing operations comprising: receiving, from the inspection device, an image of the multi-device substrate (Said Figure 2 “Scan tray/carrier image”); analyzing the image to identify defects in the image of the multi-device substrate (Said Figure 2 “Check the presence of defects”) Said Figure 2 Examiner note: This figure shows the multi die/device input, where each die/device is segmented from the image and determined to be defective or good.); and generating, as output, an indication of the defects and the one or more devices affected by the defects (Said Figure 2 “Defective die”).
Said does not teach the multi-device substrate comprising one or more regions, each region of the one or more regions having a plurality of devices of different device types formed thereon; identifying a golden die corresponding to the multi-device substrate, the golden die representing a canonical design of devices formed on the multi-device substrate and indicating a location of each device in each region of the one or more regions; analyzing the image to identify defects in the image of the multi-device substrate by comparing the image of the multi-device substrate to the golden die; and mapping locations of the identified defects to corresponding locations on the golden die.
However, Keenan teaches the multi-device substrate comprising one or more regions, each region of the one or more regions having a plurality of devices of different device types formed thereon (Keenan Section 2.2 “This provides a direct line of access (through the silicon) to the ICs transistors, since all wires and metallization are near the top of the IC.”; Section 3.2 “The influence from noise is mitigated and the image is classified into groups represented by objects on the IC, such as circuits, joints, and board background.” Examiner note: The integrated circuit of Keenan contains multiple devices such as transistors, diodes, a microprocessor, circuits, and joints as discussed with regards to the first argument on page 9 of “Remarks”.); identifying a golden die corresponding to the multi-device substrate, the golden die representing a canonical design of devices formed on the multi-device substrate and indicating a location of each device in each region of the one or more regions (Keenan Section 3.2 “Comparison - An error-free image, or a reconstructed image obtained from an IC built with a known-good-die (KGD), is used as the reference.” Examiner note: As discussed with regards to the second argument on page 9 of “Remarks”, the KGD is compared to the test die to ensure the test die contains the same devices in the same locations with the same function as the KGD. This is further supported by the disclosure of Bertin); analyzing the image to identify defects in the image of the multi-device substrate by comparing the image of the multi-device substrate to the golden die (Keenan Section 3.2 “Comparison - An error-free image, or a reconstructed image obtained from an IC built with a known-good-die (KGD), is used as the reference. Laser images are carefully compared to detect potential defects.”); and mapping locations of the identified defects to corresponding locations on the golden die (Keenan Figure 7 “Detected defects”).
Keenan is considered to be analogous to the claimed invention because they are both in the same field of defect detection on dies. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified they system of Said to include the teachings of Keenan, to provide the advantage of detecting degraded conditions of integrated circuit components, allowing for predictive capability (Keenan Section 6 “By using a laser to examine the characteristics of the integrated circuit on a microscopic level we are able acquire images depicting the actual physical condition of the internal IC components, the analysis of which is used to identify failed circuits as well as to detect degraded circuitry conditions which may be indicative of impending failure. This predictive capability would be highly desirable, and may prove useful in identifying UUTs with marginal performance that may contribute towards solving the RTOK problem.”)
In regards to claim 2, Said in view of Keenan teaches the inspection system of claim 1, further comprising: identifying a first region of the one or more regions of the multi-device substrate (Said Figure 2 “Unit Segmentation”; Section II A “Each tray/carrier image consists of multiple clusters as shown in Fig.1 where each cluster consists of several units as shown in Fig. 3(a). Fig. 3(b) shows the individual unit which consists of die, substrate, pads, and fiducial mark.”); and determining whether the first region fails inspection based on an amount and types of defects identified in the first region (Said Figure 2 “Check the presence of defects” and “Good die” or “Defective die”).
In regards to claim 3, Said in view of Keenan teaches the inspection system of claim 1, further comprising: identifying a first device of the plurality of devices formed on the multi-device substrate (Said Figure 2 “Unit Segmentation”; Section II A “Each tray/carrier image consists of multiple clusters as shown in Fig.1 where each cluster consists of several units as shown in Fig. 3(a). Fig. 3(b) shows the individual unit which consists of die, substrate, pads, and fiducial mark.”); and determining whether the first device fails inspection based on an amount and types of defects identified in a location corresponding to the first device (Said Figure 2 “Check the presence of defects” and “Good die” or “Defective die”).
In regards to claim 4, Said in view of Keenan teaches the inspection system of claim 1, wherein analyzing the image to identify defects in the image of the multi-device substrate by comparing the image of the multi-device substrate to the golden die comprises: applying a device mask to the image of the multi-device substrate, the device mask corresponding to the golden die (Keenan Figures 4-7; Section 3.2 “Comparison - An error-free image, or a reconstructed image obtained from an IC built with a known-good-die (KGD), is used as the reference. Laser images are carefully compared to detect potential defects. This method should be effective when the defects break photo-mask patterns. Image registration is a very important issue in this case.” Examiner note: As can be seen in figures 4-7, the defect free image is subtracted out from the image with potential defects, and then the difference image is masked to identify defects).
In regards to claim 5, Said in view of Keenan teaches the inspection system of claim 1, wherein analyzing the image to identify defects in the image of the multi-device substrate by comparing the image of the multi-device substrate to the golden die comprises: iteratively applying one or more region masks to the one or more regions in the image of the multi-device substrate (Keenan Figures 4-7; Section 3.2 “Comparison - An error-free image, or a reconstructed image obtained from an IC built with a known-good-die (KGD), is used as the reference. Laser images are carefully compared to detect potential defects. This method should be effective when the defects break photo-mask patterns. Image registration is a very important issue in this case.”; Said Figures 1 and 2 Examiner note: Said teaches inputting a multi-die/device image, and segmenting out each die/device for defect detection. Keenan teaches performing defect detection by using a reference defect free image to create a mask and identify defects. So, when considering Said in view of Keenan, each device/die of Keenan would undergo the defect detection method of Keenan. Therefore, these references in combination teach iteratively applying a mask to each of the dies/devices for defect detection).
In regards to claim 6, Said in view of Keenan teaches the inspection system of claim 1, wherein generating, as output, the indication of the defects and the one or more devices affected by the defects comprises: generating an annotated image of the multi-device substrate corresponding to the image of the multi-device substrate, the annotated image comprising annotations corresponding to the identified defects (Said Figures 5 and 6 “Final results” Examiner note: These figures show identifying defect and outlining them in the image).
In regards to claim 7, Said in view of Keenan teaches the inspection system of claim 6, wherein a size, a shape, or a type of annotation is based on a determined type of defect (Said Figures 5 and 6).
In regards to claim 8, Said in view of Keenan renders obvious the claim language as in the consideration of claim 1.
In regards to claim 9, Said in view of Keenan renders obvious the claim language as in the consideration of claim 2.
In regards to claim 10, Said in view of Keenan renders obvious the claim language as in the consideration of claim 3.
In regards to claim 11, Said in view of Keenan renders obvious the claim language as in the consideration of claim 4.
In regards to claim 12, Said in view of Keenan renders obvious the claim language as in the consideration of claim 5.
In regards to claim 13, Said in view of Keenan renders obvious the claim language as in the consideration of claim 6.
In regards to claim 14, Said in view of Keenan renders obvious the claim language as in the consideration of claim 7.
In regards to claim 15, Said in view of Keenan teaches a non-transitory computer readable medium having one or more sequences of instructions stored thereon, which, when executed by a processor, causes a computing system to perform operations of claim 1 (Keenan Figure 1 “Controller” and “Workstation”) and renders obvious the remaining claim language as in the consideration of claim 1.
In regards to claim 16, Said in view of Keenan renders obvious the claim language as in the consideration of claim 2.
In regards to claim 17, Said in view of Keenan renders obvious the claim language as in the consideration of claim 3.
In regards to claim 18, Said in view of Keenan renders obvious the claim language as in the consideration of claim 4.
In regards to claim 19, Said in view of Keenan renders obvious the claim language as in the consideration of claim 5.
In regards to claim 20, Said in view of Keenan renders obvious the claim language as in the consideration of claim 6.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALEB LOGAN ESQUINO whose telephone number is (703)756-1462. The examiner can normally be reached M-Fr 8:00AM-4:00PM EST.
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/CALEB L ESQUINO/Examiner, Art Unit 2677
/ANDREW W BEE/Supervisory Patent Examiner, Art Unit 2677
