Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
1. This office action is responsive to communication(s) filed on 2/9/2026.
2. Newly added claims 16-26 are presented for examination.
Response to Double Patenting Arguments
3. Applicant’s request for reconsideration and removal of the obviousness type double patenting rejection set forth in the last Office action is persuasive.
4. Applicant's arguments with respect to the newly added claims have been considered but are moot in view of the new ground(s) of rejections as follows:
Claim Rejections - 35 U.S.C. § 103
5. The following is a quotation of 35 U.S.C. § 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
6. Claims 16-21 and 23-26 are rejected under 35 U.S.C. § 103(a) as being unpatentable Patel et al. US Pub. No. 20150348594 in view of Kolar US Pub. No. 20220342576.
As per claims 16, 18, 19 and 21, Fig. 1 and a paragraph 15 of Patel are directed to a system on chip (SOC) comprising: a random-access memory (RAM) having a first inner memory bank (102-2, par. 15), a first outer memory bank (102-1), a second inner memory bank (102-3), and a second outer memory bank (309BO), wherein the first inner memory bank (Fig. 1) is positioned between the first outer memory bank and a controller (103) of the RAM, and wherein the second inner memory bank (Fig. 1) is positioned between the second outer memory bank and the controller of the RAM;
a distributed multiplexer system (104-1 and 104-2) within the RAM, including
Figs. 1-3 of Patel fail to disclose a first outer multiplexer disposed on a first side of the first inner memory bank opposite the controller and a second outer multiplexer disposed on a second side of the second inner memory bank opposite the controller; a first plurality of data lines coupling the controller to the first outer multiplexer. However, Fig. 3 of Kolar discloses a first outer multiplexer (308A(1)-308A(4), par. 40) disposed on a first side of the first inner memory bank (309AI, par. 42) opposite the controller (320) and a second outer multiplexer (308A(1)-308A(4), par. 42) disposed on a second side of the second inner memory bank (309B1, par. 46) opposite the controller (320); a first plurality of data lines (bitlines, par. 44) coupling the controller to the first outer multiplexer. It would have been obvious to a person of ordinary skill in the art at the time invention was made to modify Patel’s memory array which utilizes the first and second outer multiplexer for the first and second inner memory banks as taught by Kolar in order to improve array access time (par. 19).
As per claim 17, Fig. 3 of Patel disclose wherein the first plurality of data lines (120) traverse the first inner memory bank (120-2), and the second plurality of data lines (130) )are physically shorter than the first plurality of data lines.
As per claim 19, Fig. 2 of Patel discloses further comprising: a third plurality of data lines (140) coupling the controller to the second outer multiplexer (see claim 1), the third plurality of data lines traversing the second inner memory bank.
As per claim 20, Fig. 3 of Patel disclose further comprising: a fourth plurality of data lines (150) coupling the controller to the second inner multiplexer, the fourth plurality of data lines being physically shorter than the third plurality of data lines.
As per claims 23-24, Figs. 1-3 of Patel discloses wherein the first outer multiplexer includes a first read multiplexer and a first write multiplexer (Fig. 3), and wherein the first inner multiplexer includes a second read multiplexer and a second write multiplexer (Fig. 3).
As per claim 25, Figs. 2-3 of Patel discloses wherein the first inner multiplexer and the second inner multiplexer are both disposed within the controller.
As per claim 26, Figs. 1-3 of Patel disclose a first local data path (120-1) associated with the first outer memory bank (102-1), the first local data path including a first precharge circuit (inherence in the memory cell device to precharge the bitlines before a reading or writing operation) and the first outer multiplexer; and a second local data path ( 130-1) associated with the first inner memory bank, the second local data path including a second precharge circuit (inherence in the memory cell device to precharge the bitlines before a reading or writing operation) and the first inner multiplexer.
It is noted that the first and second precharge would be rejected under 103 rejection further in view of Kolar et al. US Pub. No. 20220383945 by paragraphs 16 and 35.
7. Claim 22 is rejected under 35 U.S.C. § 103(a) as being unpatentable Patel et al. US Pub. No. 20150348594 in view of Kolar US Pub. No. 20220342576 and further in view of Namekawa US Pub. No. 20080165564.
Figs. 1-3 of Patel discloses wherein the first plurality of data lines includes a first read data line and a first write data line (Fig. 3) but Patel and Kolar fail to disclose wherein the first read data line has a different width than does the first write data line. However, Fig. 6C, a paragraph 87 and a claim 13 of Namekawa disclose wherein the first read data line (RBLc or RBLt) has a different width than does the first write data line (WBLn<0>). It would have been obvious to a person of ordinary skill in the art at the time invention was made to modify Patel and Kolar's memory array which utilizes the different width of the read and write data line in order to have a large current may thus be supplied during the writing, thereby providing a good writing condition. In addition, a small current may be efficiently amplified during the reading, thereby providing rapid and accurate reading characteristics (par. 87).
Response to Arguments
8. Applicant's arguments with respect to the newly added claims have been considered but are moot in view of the rejections as set forth in the rejection above.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
9. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V HO whose telephone number is (571)272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Thursday and Friday of the first week of a bi-week and Tuesday and Wednesday of the second week.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300.
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/HOAI V HO/Primary Examiner, Art Unit 2827