DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Objections
Claim 1 is objected to because of the following informalities: in line 15 of the claim, correct the typographical error “retrieveg”.
Claim 7 is objected to because of the following informalities: the acronym “FLC” in line 6 of the claim has not been previously spelled out; the “a final level cache control” does not indicate an acronym relationship (e.g., ‘a final level cache (FLC)’) and the term “control” is not consistent with the subsequent term “controller”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-6 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Malladi’830 et al. (US Pub. No. 2018/0210830), hereinafter referred to as Malladi’830’830.
Referring to claim 1, Malladi’830 discloses a memory system (fig. 2) comprising: a processor (fig. 2, 200), having a processor cache (host processor and the hybrid cache memory, [0020]), which generates a data request for requested data, the requested data identified by a data address (logical-to-physical address table map, [0044]; memory address/banks, [0047]); an interposer layer (fig. 2, 210 interposer) on which the processor resides, the interposer layer providing a communication channel between the processor and other elements of the memory system (fig. 2, [0040]); a memory stack comprising one or more layers of stacked memory dies (fig. 2, HBM 222 stack), the memory stack located on a base die (fig. 2, Logic Die); the base die on the interposer layer, the base die in communication with the processor and the memory stack (fig. 2, [0041-0047]), the base die further comprising: a final level cache controller (cache controller 220, [0041]) which is part of the base die and in communication with the processor, the final level cache controller configured to: receive the data request for requested data; process the data request to determine if the requested data is stored in the memory stack; responsive to the requested data being stored in the memory stack, retrieving the requested data and transmit the requested data to the processor (a cache hit, [0046]); responsive to the requested data not being stored in the memory stack: retrieving the requested data from an external memory (Upon cache miss in the HBM 222, the cache controller may access the non-volatile memory die 226 to obtain the data line, [0046]; NOTE: “external” is an ambiguous term, the NVM 226 is external to processor 200 and external to the HBM 200 memory stack); transmitting the requested data to the processor (the cache controller 220 incorporates firmware logic allowing it to control (e.g., write to and read from) the one or more non-volatile memory dies 226 as well as the one or more stacks of HBM dies, [0044]; cache controller…servicing a host command, such as a host read or write command, [0053]); storing the requested data in the memory stack (NOTE: Malladi’830 teaches the cache controller servicing host reads in [0053], anticipates cache misses in [0046], and teaches caching actively used information in [0037]; one or ordinary skill in the art would recognize the further storing of the missed data in the cache as a fundamental function of a cache read miss operation for data being actively used in response to the read command); and a memory stack interface configured to enable communication between the memory stack and the final level cache controller (the cache controller 220 incorporates firmware logic allowing it to control (e.g., write to and read from) the one or more non-volatile memory dies 226 as well as the one or more stacks of HBM dies 222, [0044]).
As to claim 2, Malladi’830 discloses the memory stack comprises high bandwidth memory (HBM) format memory (fig. 2, HBM 222 stack).
As to claim 3, Malladi’830 discloses the external memory comprises a shared memory pool (a hybrid logical-to-physical address table map (hybrid LtoP table), which tracks in what physical location of the one or more stacks of HBM dies 222 and/or the one or more non-volatile memory dies 226 each piece of stored data is located. The cache controller 220 may act as an interface block between the host 200 and the memory blocks within the hybrid cache memory 220 and, in some embodiments, may allow the host 200 to be blind to (e.g., be unaware of) the existence of the one or more non-volatile memory dies 226, while availing itself of the benefits provided by the one or more non-volatile memory dies 226, [0044]).
As to claim 5, Malladi’830 discloses a printed circuit board (a printed circuit board (PCB), [0062]; fig. 2, Package Substrate 212) supporting and electrically connected to the interposer layer and the external memory (interposer 210 may physically support the host 200 and the hybrid cache memory 202 and allow them to electrically interface with one another though the first and second set of vias 204 and 206 and to electrically interface with peripheral components external to (e.g., outside the packaging of) the processing device 100 through the third set of vias 208, a package substrate 212, and package pins 214, [0040]).
As to claim 6, Malladi’830 discloses the memory stacks, the base die, the interposer layer and the processor are located in the same package (fig. 2, HBM stack 222, Logic Die 220, interposer 210, and processor 200 are located in “the same package” created by the Package Substrate 212).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-10 and 12-18 are rejected under 35 U.S.C. 102(a)(1) as anticipated by Malladi’830 or, in the alternative, under 35 U.S.C. 103 as obvious over Malladi’830 in view of Mehrotra et al. (US Pub. No. 2014/0281169), hereinafter referred to as Mehrotra.
Referring to claim 7, Malladi’830 discloses a method of operating a data access system (fig. 2), wherein the data access system comprises a base die(fig. 2, Logic Die) having a final level cache control with a memory stack controller (fig. 2, cache controller 220, [0041]), and memory stack (fig. 2, HBM 222 stack) accessible through the memory stack controller and external memory (fig. 2, Flash die 226 , [0046]; NOTE: “external” is an ambiguous term, the NVM 226 is external to processor 200 and external to the HBM 200 memory stack), the method comprising: receiving, from a requesting element, a request for data which includes a physical address (logical-to-physical address table map, [0044]; memory address/banks, [0047]; servicing a host command, such as a host read or write command, [0053]); providing the request for data to the FLC controller on the base die (the cache controller 220 incorporates firmware logic allowing it to control (e.g., write to and read from) the one or more non-volatile memory dies 226 as well as the one or more stacks of HBM dies, [0044]; cache controller…servicing a host command, such as a host read or write command, [0053]); determining if the FLC controller contains the physical address corresponding to the data (The cache controller 220 may maintain a hybrid logical-to-physical address table map (hybrid LtoP table), which tracks in what physical location of the one or more stacks of HBM dies 222 and/or the one or more non-volatile memory dies 226 each piece of stored data is located, [0044]); responsive to the FLC controller containing the physical address, retrieving the data from the memory stack and providing the data to the from a requesting element (a cache hit, [0046]); responsive to the FLC controller not containing the physical address: forwarding the request for data and the physical address to the external memory; retrieving the data from the external memory (Upon cache miss in the HBM 222, the cache controller may access the non-volatile memory die 226 to obtain the data line, [0046]); providing the data to the FLC controller, the FLC controller: stores the data in the memory stack (NOTE: Malladi’830 teaches the cache controller servicing host reads in [0053], anticipates cache misses in [0046], and teaches caching actively used information in [0037]; one or ordinary skill in the art would recognize the further storing of the missed data in the cache as a fundamental function of a cache read miss operation for data being actively used in response to the read command); and updating a tag designating the recent use of the data (NOTE: Malladi’830 teaches deleting “older data or least frequently used data” the “earliest (or least) accessed data”, [0045] and [0051], which implies information must be maintained for determining the recency of the data use, and the claimed “a tag” is a generic term for associated information, which would be taught by the implied information necessary to facilitate the deletion determination anticipated by Malladi’830).
Furthermore, Mehrotra teaches updating a tag designating the recent use of the data (If there is a cache hit, the LRU field of the cache tag 704 corresponding to the data requested is updated; [0140]).
Malladi’830 and Mehrotra are analogous art because they are from the same field of endeavor, cache management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Malladi’830 and Mehrotra before him or her, to modify the storage system of Malladi’830 to include the cache tag of Mehrotra because Malladi’830 and Mehrotra demonstrate the prior art included each element claimed, and Malladi’830 has been shown to contained a device (method, product, etc.) which differed from the claimed device by not explicitly indicating the embodiment of “a tag” which could be considered a possible substitution of one usage frequency information for another; Mehortra explicitly teaches that the substituted components and their functions were known in the art; and one of ordinary skill in the art could have substituted one embodiment of usage frequency information for another, and the results of the substitution would have been a predictable indication of usage recency.
The rationale to support a conclusion that the claim would have been obvious is that the substitution of one known element for another yields predictable results to one of ordinary skill in the art (MPEP 2143.I.B).
Therefore, it would have been obvious to combine Malladi’830 and Mehrotra to obtain the invention as specified in the instant claim.
As to claim 8, Malladi’830 discloses the FLC controller comprises a look-up table with physical addresses that correspond to physical location in the memory stack (logical-to-physical address table map, [0044]; memory address/banks, [0047]; servicing a host command, such as a host read or write command, [0053]).
As to claim 9, Malladi’830 discloses the memory stack comprises a HBMx variant type memory stack (fig. 2, HBM 222 stack).
As to claim 10, Malladi’830 discloses the external memory comprises a shared memory pool (a hybrid logical-to-physical address table map (hybrid LtoP table), which tracks in what physical location of the one or more stacks of HBM dies 222 and/or the one or more non-volatile memory dies 226 each piece of stored data is located. The cache controller 220 may act as an interface block between the host 200 and the memory blocks within the hybrid cache memory 220 and, in some embodiments, may allow the host 200 to be blind to (e.g., be unaware of) the existence of the one or more non-volatile memory dies 226, while availing itself of the benefits provided by the one or more non-volatile memory dies 226, [0044]).
As to claim 12, Malladi’830 discloses an interposer layer (fig. 2, memory substrate 230) between the base die and the external memory such that the data passes through the interposer layer from the external memory to the requesting element (the cache controller 220 incorporates firmware logic allowing it to control (e.g., write to and read from) the one or more non-volatile memory dies 226, [0044]; cache controller…servicing a host command, such as a host read or write command, [0053]).
Referring to claim 13, Malladi’830 discloses a memory system (fig. 2) operating under the HBM (high bandwidth memory) standard (HBM, [0005]) comprising: a memory stack comprising one or more layers of stacked memory dies (fig. 2, HBM 222 stack), the memory stack located on a base die (fig. 2, Logic Die); a memory stack controller (fig. 2, 220, [0041]), located with the memory stack or on the base die; the base die in communication with the memory stack, the base die further comprising: final level cache controller (fig. 2, cache controller 220, [0041]) to: receive the data request for requested data from a requesting element; process the data request to determine if the requested data is stored in the memory stack; responsive to the requested data being stored in the memory stack: retrieving the requested data from the memory stack (a cache hit, [0046]); transmitting the requested data to the requesting element (the cache controller 220 incorporates firmware logic allowing it to control (e.g., write to and read from) the one or more non-volatile memory dies 226 as well as the one or more stacks of HBM dies, [0044]; cache controller…servicing a host command, such as a host read or write command, [0053]), and updating a recently used tag associated with the requested data (NOTE: Malladi’830 teaches deleting “older data or least frequently used data” the “earliest (or least) accessed data”, [0045] and [0051], which implies information must be maintained for determining the recency of the data use, and the claimed “a tag” is a generic term for associated information, which would be taught by the implied information necessary to facilitate the deletion determination anticipated by Malladi’830); responsive to the requested data not being stored in the memory stack: retrieving the requested data from an external memory (Upon cache miss in the HBM 222, the cache controller may access the non-volatile memory die 226 to obtain the data line, [0046]; NOTE: “external” is an ambiguous term, the NVM 226 is external to processor 200 and external to the HBM 200 memory stack); transmitting the requested data to the requested element; and storing the requested data in the memory stack at an empty memory space (it is determined that there is sufficient space within the one or more stacks of HBM 222, [0051]) or by replacing the least most recently used data in memory (deleting earliest accessed data stored at the HBM so as to create sufficient space, [0022]; NOTE: Malladi’830 teaches the cache controller servicing host reads in [0053], anticipates cache misses in [0046], and teaches caching actively used information in [0037]; one or ordinary skill in the art would recognize the further storing of the missed data in the cache as a fundamental function of a cache read miss operation for data being actively used in response to the read command).
Furthermore, Mehrotra teaches updating a tag designating the recent use of the data (If there is a cache hit, the LRU field of the cache tag 704 corresponding to the data requested is updated; [0140]).
Malladi’830 and Mehrotra are analogous art because they are from the same field of endeavor, cache management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Malladi’830 and Mehrotra before him or her, to modify the storage system of Malladi’830 to include the cache tag of Mehrotra because Malladi’830 and Mehrotra demonstrate the prior art included each element claimed, and Malladi’830 has been shown to contained a device (method, product, etc.) which differed from the claimed device by not explicitly indicating the embodiment of “a tag” which could be considered a possible substitution of one usage frequency information for another; Mehortra explicitly teaches that the substituted components and their functions were known in the art; and one of ordinary skill in the art could have substituted one embodiment of usage frequency information for another, and the results of the substitution would have been a predictable indication of usage recency.
The rationale to support a conclusion that the claim would have been obvious is that the substitution of one known element for another yields predictable results to one of ordinary skill in the art (MPEP 2143.I.B).
Therefore, it would have been obvious to combine Malladi’830 and Mehrotra to obtain the invention as specified in the instant claim.
As to claim 14, Malladi’830 discloses the requesting element comprises a central processing unit (CPU) or graphical processing unit (GPU) (fig. 2, CPU/CPU 200).
As to claim 15, Malladi’830 discloses the memory stack consists of 1, 2, or 4 memory dies (1-4 HBMs depicted in fig. 2).
As to claim 16, Malladi’830 discloses the requesting element is a processor electrically connected to the base die, the processor configured to generate the data request (fig. 2, CPU 220, [0053]).
As to claim 17, Malladi’830 discloses an interposer layer such that the base die and the requesting element are on the interposer layer and electrically connect through the interposer layer (fig. 2, 210, [0040]).
As to claim 18, Malladi’830 discloses the external memory is shared pooled memory (a hybrid logical-to-physical address table map (hybrid LtoP table), which tracks in what physical location of the one or more stacks of HBM dies 222 and/or the one or more non-volatile memory dies 226 each piece of stored data is located. The cache controller 220 may act as an interface block between the host 200 and the memory blocks within the hybrid cache memory 220 and, in some embodiments, may allow the host 200 to be blind to (e.g., be unaware of) the existence of the one or more non-volatile memory dies 226, while availing itself of the benefits provided by the one or more non-volatile memory dies 226, [0044]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Malladi’830 in view of Malladi et al. (US Pub. No. 2021/0311900), hereinafter referred to as Malladi’900.
As to claim 4, Malladi’830 does not appear to explicitly disclose retrieving the requested data from an external memory occurs over a computer express link (CXL) memory connection.
However, Malladi’900 discloses retrieving the requested data from an external memory occurs over a computer express link (CXL) memory connection (Each memory module may have a CXL interface and include an interface circuit for translating between CXL packets and signals suitable for the memory in the memory module 135. In some embodiments, these interface circuits are instead in the enhanced capability CXL switch 130, and each of the memory modules 135 has an interface that is the native interface of the memory in the memory module 135, [0056]).
Malladi’830 and Malladi’900 are analogous art because they are from the same field of endeavor, cache management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Malladi’830 and Malladi’900 before him or her, to modify the memory system of Malladi’830 to include the CXL interface of Malladi’900 because Malladi’830 has been shown to contained a device (method, product, etc.) which differed from the claimed device by the substitution of one memory interface with another; Malladi’900 explicitly teaches that the substituted component (i.e., CXL interface) and its functions were known in the art; and one of ordinary skill in the art could have substituted one memory interface for another, and the results of the substitution would have been a predictable storage system interfacing.
The rationale to support a conclusion that the claim would have been obvious is that the substitution of one known element for another yields predictable results to one of ordinary skill in the art (MPEP 2143.I.B).
Therefore, it would have been obvious to combine Malladi’830 and Malladi’900 to obtain the invention as specified in the instant claim.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Malladi’830 in view of Malladi’900; or over Malladi’830 in view of Mehrotra, further in view of Malladi’900.
As to claim 11, Malladi’830 does not appear to explicitly disclose the external memory comprises switch connected memory.
However, Malladi’900 discloses the external memory comprises switch connected memory (Each memory module may have a CXL interface and include an interface circuit for translating between CXL packets and signals suitable for the memory in the memory module 135. In some embodiments, these interface circuits are instead in the enhanced capability CXL switch 130, and each of the memory modules 135 has an interface that is the native interface of the memory in the memory module 135, [0056]).
Malladi’830 and Malladi’900 are analogous art because they are from the same field of endeavor, cache management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Malladi’830 and Malladi’900 before him or her, to modify the memory system of Malladi’830 to include the CXL switch of Malladi’900 because Malladi’830 has been shown to contained a device (method, product, etc.) which differed from the claimed device by the substitution of one memory interconnect with another; Malladi’900 explicitly teaches that the substituted component (i.e., CXL switch) and its functions were known in the art; and one of ordinary skill in the art could have substituted one memory interconnect for another, and the results of the substitution would have been a predictable storage system interconnect.
The rationale to support a conclusion that the claim would have been obvious is that the substitution of one known element for another yields predictable results to one of ordinary skill in the art (MPEP 2143.I.B).
Therefore, it would have been obvious to combine Malladi’830 and Malladi’900 to obtain the invention as specified in the instant claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The Stocksdale et al. article Architecting HBM as a High Bandwidth, High Capacity, Self-Managed Last-Level Cache and the US Pub. No. 2022/0308998 of Sasanka et al. are pertinent to HBM cache architecture.
The examiner has cited particular column, line, and/or paragraph numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in its entirety as potentially teaching of all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC T OBERLY whose telephone number is (571)272-6991. The examiner can normally be reached on M-F 800am-430pm (MT).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on (571) 272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Center. For more information about the Patent Center, see https://patentcenter.uspto.gov/. Should you have questions on access to the Patent Center system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIC T OBERLY/ Primary Examiner, Art Unit 2184