DETAILED ACTION
This office action is in response to the application filed on 5/20/2024. Claim(s) 1-20 is/are pending and are examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority/Benefit
Applicant’s priority claim is hereby acknowledged of PRO 63/503,651 05/22/2023, which papers have been placed of record in the file.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 8-10 and 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Radovanovic (US 2025/0291739 A1), in view of Smith (US 2011/0004807 A1).
Regarding claims 1, 8 and 15, Radovanovic teaches:
“A method (Radovanovic, ¶ 32, 35 and 48 teaches implementation with a processor, memory and medium) comprising: reading a firmware image from a memory device (Radovanovic, Figs. 2, 4, ¶ 23-25 and 30, the additional firmware stored on NVM 250 is read); aggregating data for the firmware image (Radovanovic, ¶ 24 the security firmware version information for additional firmware is read); receiving a first authentication code associated with the firmware image (Radovanovic, Figs. 2, 4, ¶ 23-25 and 30, the hash values are compared to determine if they match);
computing a second authentication code by performing a cryptographic operation (Radovanovic, Figs. 2, 4, ¶ 16, 20, 23-25 and 30, teaches computing a cryptographic hash on the firmware image); determining the first authentication code and the second authentication code match (Radovanovic, Figs. 2, 4, ¶ 23-25 and 30, the hash values are compared to determine if they match); and loading the firmware image onto the memory device in response to determining that the first authentication code and the second authentication code match (Radovanovic, Figs. 2, 4, ¶ 25 and 30, the additional firmware image is loaded into memory. Examiner’s note: instant specification ¶ 42 and associated figures depict and describe that multiple distinct memory systems are encompassed in a larger memory framework)”.
Radovanovic does not, but in related art, Smith Fig. 2A ¶ 27-31 teaches aggregating parity information for code stored in memory and hashing that information for validation with another hash value.
Before applicant’s earliest effective filing it would have been obvious to one of ordinary skill in the art, having the teachings of Radovanovic and Smith, to modify the firmware validation system of Radovanovic to include the method to hash parity information of code as taught in Smith. The motivation to do so constitutes applying a known technique to known devices and/or methods ready for improvement to yield predictable results.
Regarding claims 2 and 9, Radovanovic and Smith teaches:
“The method of claim 1 (Radovanovic and Smith teaches the limitations of the parent claims as discussed above), wherein performing the cryptographic operation on the parity data comprises: performing a hash operation on the parity data (Smith Fig. 2A ¶ 27-31 teaches aggregating parity information for code stored in memory and hashing that information for validation with another hash value)”.
Regarding claims 3, 10, and 16, Radovanovic and Smith teaches:
“The method of claim 2 (Radovanovic and Smith teaches the limitations of the parent claims as discussed above), wherein performing the hash operation on the parity data uses a cryptographic key (Smith ¶ 31 teaches standard hashing with a key)”.
Claim(s) 4-6, 11-13, and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Radovanovic in view of Smith in view of Cariello (US 2020/0210586 A1).
Regarding claims 4, 11, and 17, Radovanovic and Smith teaches:
“The method of claim 1 (Radovanovic and Smith teaches the limitations of the parent claims as discussed above)”.
Radovanovic and Smith does not, but in related art, Cariello teaches:
“wherein detecting an uncorrectable error in the firmware image triggers a rejection of the firmware image (Cariello, Figs. 6, 8, ¶ 78 and 89 teaches reading sections of the firmware image and checking the parity, the hash value and determining an uncorrectable error and rejecting the firmware when that error places the number of errors over a threshold)”.
Before applicant’s earliest effective filing it would have been obvious to one of ordinary skill in the art, having the teachings of Radovanovic, Cariello and Smith, to modify the firmware validation system of Radovanovic and Smith to include the method check the firmware, the code and sections of the firmware for uncorrectable errors as taught in Cariello. The motivation to do so constitutes applying a known technique to known devices and/or methods ready for improvement to yield predictable results.
Regarding claims 5, 12, and 18, Radovanovic and Smith teaches:
“The method of claim 1 (Radovanovic and Smith teaches the limitations of the parent claims as discussed above)”.
Radovanovic and Smith does not, but in related art, Cariello teaches:
“wherein detecting an uncorrectable error in the first authentication code triggers a rejection of the firmware image (Cariello, Figs. 6, 8, ¶ 78 and 89 teaches reading sections of the firmware image and checking the parity, the hash value and determining an uncorrectable error and rejecting the firmware when that error places the number of errors over a threshold)”.
Before applicant’s earliest effective filing it would have been obvious to one of ordinary skill in the art, having the teachings of Radovanovic, Cariello and Smith, to modify the firmware validation system of Radovanovic and Smith to include the method check the firmware, the code and sections of the firmware for uncorrectable errors as taught in Cariello. The motivation to do so constitutes applying a known technique to known devices and/or methods ready for improvement to yield predictable results.
Regarding claims 6, 13 and 19, Radovanovic and Smith teaches:
“The method of claim 1 (Radovanovic and Smith teaches the limitations of the parent claims as discussed above)”.
Radovanovic and Smith does not, but in related art, Cariello teaches:
“wherein the firmware image comprises a plurality of portions, wherein reading the firmware image from the memory device comprises reading the plurality of portions, and wherein computing the parity data of the firmware image comprising computing a parity data portion for a portion of the plurality of portions (Cariello, Figs. 6, 8, ¶ 78 and 89 teaches reading sections of the firmware image and checking the parity, the hash value and determining an uncorrectable error and rejecting the firmware when that error places the number of errors over a threshold)”.
Before applicant’s earliest effective filing it would have been obvious to one of ordinary skill in the art, having the teachings of Radovanovic, Cariello and Smith, to modify the firmware validation system of Radovanovic and Smith to include the method check the firmware, the code and sections of the firmware for uncorrectable errors as taught in Cariello. The motivation to do so constitutes applying a known technique to known devices and/or methods ready for improvement to yield predictable results.
Claim(s) 7, 14 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Radovanovic in view of Smith in view of Prabhu (US 2021/0141703 A1).
Regarding claims 7, 14 and 20, Radovanovic and Smith teaches:
“The method of claim 1 (Radovanovic and Smith teaches the limitations of the parent claims as discussed above)”.
Radovanovic in view of Smith does not, but in related art, Prabhu teaches:
“wherein the parity data is a low-density parity check code and wherein computing the parity data comprises reading the low-density parity check code from the memory device (Prabhu, ¶ 54 teaches a low density a parity check of memory using the firmware)”.
Before applicant’s earliest effective filing it would have been obvious to one of ordinary skill in the art, having the teachings of Radovanovic, Prabhu and Smith, to modify the firmware validation system of Radovanovic and Smith to include the method use a low density parity check as taught in Prabhu. The motivation to do so constitutes applying a known technique to known devices and/or methods ready for improvement to yield predictable results.
Conclusion
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure: See PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Stephen T Gundry whose telephone number is (571) 270-0507. The examiner can normally be reached Monday-Friday 9AM-5PM (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joseph Hirl can be reached on (571) 272-3685. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEPHEN T GUNDRY/Primary Examiner, Art Unit 2435