DETAILED ACTION
This Office action is in response to the application filed on May 20, 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on May 20, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings were filed on May 20, 2024. These drawings are accepted by the Examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by IMANISHI et al. (U.S. Pub. 2023/0208185 A1).
In re claim 1, IMANISHI discloses (Figs. 1-4) a cascade converter (100), comprising:
a main control system (control circuit 28), a plurality of power modules (P1-Pn), and a bypass circuit (B0) corresponding to each power module;
wherein the main control system is communicatively connected to each power module, the power modules are electrically connected in turn, and any one of the power modules has at least one communicable power module, the communicable power module is an else power module communicatively connected to the power module, and the number of power modules spaced apart is within a preset value (Para. 0026-0031);
when the power module is faulted, the power module on which a fault occurs is a faulty power module, the faulty power module sends a fault signal to the main control system (Para. 0057-0059 and 0064-0066);
the main control system generates a bypass command according to the fault signal and sends same to the faulty power module and the communicable power module of the faulty power module (Para. 0057-0059 and 0064-0066);
the communicable power module generates a first bypass signal according to the bypass command and outputs same to the faulty power module; the faulty power module controls, according to the bypass command and/or the first bypass signal, the corresponding bypass circuit to bypass the faulty power module (Para. 0057-0059 and 0064-0066).
In re claim 2, IMANISHI discloses wherein each power module receives a feedback signal of the corresponding bypass circuit and sends the feedback signal to the main control system, the main control system makes a state confirmation for each bypass circuit according to the feedback signal (Para. 0024-0031).
In re claim 3, IMANISHI discloses wherein the main control system determines, according to the feedback signal, whether the faulty power module that needs to be bypassed has been bypassed, and generates a start/stop command according to whether the faulty power module has been bypassed, the start/stop command is used for controlling the cascade converter to restart or stop (Para. 0024-0031, 0057-0059 and 0064-0066).
In re claim 4, IMANISHI discloses wherein the power module further receives a feedback signal of the corresponding communicable power module and sends same to the main control system (Para. 0024-0031).
In re claim 5, IMANISHI discloses (Fig. 3) wherein each power module comprises a signal control circuit (45) and a signal processing circuit (comprising 40, 41, 42, 43 and 44);
the signal control circuit is electrically connected to the signal processing circuit, the signal processing circuit is electrically connected to the bypass circuit, and the signal control circuit is communicatively connected to the main control system (Para. 0056-0073); and
signal processing circuits in two adjacent power modules are electrically connected (Para. 0056-0073);
the signal control circuit of the communicable power module of the faulty power module receives the bypass command sent by the main control system and transmits the bypass command to the signal processing circuit of the communicable power module, and the signal processing circuit of the communicable power module generates the first bypass signal and transmits same to the signal processing circuit of the faulty power module (Para. 0056-0073);
the signal control circuit of the faulty power module transmits the bypass command to the signal processing circuit of the faulty power module, and the signal processing circuit of the faulty power module generates a second bypass signal according to the bypass command and generates a bypass drive signal according to the first bypass signal or the second bypass signal (Para. 0056-0073).
Allowable Subject Matter
Claims 6-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 6, the prior art of record fails to disclose or suggest “wherein the signal processing circuit comprises a first transmission circuit, a first signal conversion circuit and a first level matching circuit; the first transmission circuit is connected to the signal control circuit of the power module, and is configured to perform isolation processing on the bypass command transmitted by the signal control circuit of the power module and output the first bypass signal to the signal processing circuit of the else power module; the first signal conversion circuit is connected to the signal processing circuit of the else power module, and is configured to receive the first bypass signal output by the signal processing circuit of the else power module and perform signal conversion on the first bypass signal to output a third bypass signal; the first level matching circuit is connected to the signal control circuit of the power module, and is configured to perform level matching on the bypass command transmitted by the signal control circuit of the power module and output a second bypass signal” in combination with other limitations of the claim. Claims 7-9 depend directly or indirectly from claim 6 and are, therefore, also objected at least for the same reasons set above.
Regarding to claim 10, the prior art of record fails to disclose or suggest “wherein the signal processing circuit of each power module receives the feedback signal of the corresponding bypass circuit, generates a first detection signal according to the feedback signal and transmits same to the signal control circuit of the power module, and the signal control circuit of the power module encodes the first detection signal and then outputs same to the main control system, the main control system makes a state confirmation for each bypass circuit according to the encoded first detection signal” in combination with other limitations of the claim. Claims 11-15 depend directly or indirectly from claim 10 and are, therefore, also objected at least for the same reasons set above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAFAEL O. DE LEÓN DOMENECH whose telephone number is (571)270-0517. The examiner can normally be reached 8:00 a.m. -5:00 p.m..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hammond Crystal can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RAFAEL O DE LEON DOMENECH/Primary Examiner, Art Unit 2838