DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 – 11 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3 – 7, 9, 10, and 14 - 16 of copending Application No. 18,801,892, Fujimori et al (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in this application are boarder than the claims in Fujimori et al 18,801892.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Regarding claim 1 Fujimori et al discloses of applicant’s A photoelectric conversion device comprising: a plurality of pixels each including: a sensor portion configured to emit a pulse corresponding to an incident photon; a counter configured to count the number of pulses; and a memory configured to store a count value of the counter; one or more memories storing instructions; and one or more processors executing the instructions to generate a signal based on a difference in the count value of the counter between at a start timing and at an end timing of an accumulation period, and output the signal generated in a first accumulation period between an end of the first accumulation period and an end of a second accumulation period, the first accumulation period and the second accumulation period being included in a full frame period, the first accumulation period being shorter than the second accumulation period (claim 1, A photoelectric conversion device comprising: a plurality of pixels each including a photoelectric conversion unit that emits pulses corresponding to photons, a counter that counts the number of the pulses, and a memory that stores a count value of the counter; one or more memories storing instructions; and one or more processors executing the instructions to generate a signal based on a difference between a count value of the counter at the start of an accumulation period and a count value at the end of the accumulation period, perform control so that a signal generated in a first accumulation period is output between the end of the first accumulation period and the end of a second accumulation period, wherein one full frame period includes the first accumulation period and the second accumulation period longer than the first accumulation period).
Regarding claim 2 Fujimori et al further discloses of applicant’s wherein the first accumulation period and the second accumulation period overlap each other (claim 3, wherein the first accumulation period and the second accumulation period overlap each other).
Regarding claim 3 Fujimori et al further discloses of applicant’s wherein the first accumulation period and the second accumulation period start at the same time (claim 4, wherein the first accumulation period and the second accumulation period start simultaneously).
Regarding claim 4 Fujimori et al further discloses of applicant’s wherein an end timing of the second accumulation period matches an end timing of the full frame period (claim 5, wherein the end of the second accumulation period coincides with the end of the full frame period).
Regarding claim 5 Fujimori et al further discloses of applicant’s wherein the one or more processors further execute the instructions to recognize a subject based on at least the signal generated in the first accumulation period (claim 6, wherein the one or more processors further execute the instructions to recognize a subject based on signals generated at least in the first accumulation period in the recognition processing).
Regarding claim 6 Fujimori et al further discloses of applicant’s wherein the one or more processors further execute the instructions to recognize the subject additionally based on the signal generated in the second accumulation period (claim 7, wherein the one or more processors further execute the instructions to further recognize the subject based on signals generated in the second accumulation period in the recognition processing).
Regarding claim 7 Fujimori et al further discloses of applicant’s wherein the one or more processors further execute the instructions to display at least the signal generated in the second accumulation period as an image (claim 9, further comprising a display unit displaying signals generated at least in the second accumulation period as an image).
Regarding claim 8 Fujimori et al further discloses of applicant’s wherein the sensor portion includes an avalanche photodiode (claim 10, wherein the photoelectric conversion unit includes an avalanche photodiode).
Regarding claim 9 Fujimori et al further discloses of applicant’s A movable apparatus comprising: a plurality of pixels each including: a sensor portion configured to emit a pulse corresponding to an incident photon; a counter configured to count the number of pulses; and a memory configured to store a count value of the counter; one or more memories storing instructions; and one or more processors executing the instructions to generate a signal based on a difference in the count value of the counter between at a start timing and at an end timing of an accumulation period, output the signal generated in a first accumulation period between an end of the first accumulation period and an end of a second accumulation period, the first accumulation period and the second accumulation period being included in a full frame period, the first accumulation period being shorter than the second accumulation period, and control an operation of the movable apparatus (claim 14, A movable apparatus comprising: a plurality of pixels each including a photoelectric conversion unit that emits pulses corresponding to photons, a counter that counts the number of the pulses, and a memory that stores a count value of the counter; one or more memories storing instructions; and one or more processors executing the instructions to generate a signal based on a difference between a count value of the counter at the start of an accumulation period and a count value at the end of the accumulation period, perform control so that a signal generated in a first accumulation period is output between the end of the first accumulation period and the end of a second accumulation period, wherein one full frame period includes the first accumulation period and the second accumulation period longer than the first accumulation period, perform recognition processing based on an image signal, and change a frequency of recognition within the one full frame period based on subject information in the recognition processing, wherein an operation of the movable apparatus is controlled based on a recognition result of the recognition processing).
Regarding claim 10 Fujimori et al further discloses of applicant’s A photoelectric conversion method of performing photoelectric conversion in a plurality of pixels each including a sensor portion configured to emit a pulse corresponding to an incident photon, a counter configured to count the number of pulses, and a memory configured to store a count value of the counter, the photoelectric conversion method comprising: generating a signal based on a difference in the count value of the counter between at a start timing and at an end timing of an accumulation period; and outputting the signal generated in a first accumulation period between an end of the first accumulation period and an end of a second accumulation period, the first accumulation period and the second accumulation period being included in a full frame period, the first accumulation period being shorter than the second accumulation period (claim 15, A method of controlling a photoelectric conversion device including a plurality of pixels each including a photoelectric conversion unit that emits pulses corresponding to photons, a counter that counts the number of the pulses, and a memory that stores a count value of the counter, the method comprising: generating a signal based on a difference between a count value of the counter at the start of an accumulation period and a count value at the end of the accumulation period; performing control so that a signal generated in a first accumulation period is output between the end of the first accumulation period and the end of a second accumulation period, and one full frame period includes the first accumulation period and the second accumulation period longer than the first accumulation period).
Regarding claim 11 Fujimori et al further discloses of applicant’s A non-transitory computer-readable storage medium configured to store a computer program comprising instructions for executing a photoelectric conversion process of performing photoelectric conversion in a plurality of pixels each including a sensor portion configured to emit a pulse corresponding to an incident photon, a counter configured to count the number of pulses, and a memory configured to store a count value of the counter, the photoelectric conversion process comprising: generating a signal based on a difference in the count value of the counter between at a start timing and at an end timing of an accumulation period; and outputting the signal generated in a first accumulation period between an end of the first accumulation period and an end of a second accumulation period, the first accumulation period and the second accumulation period being included in a full frame period, the first accumulation period being shorter than the second accumulation period (claim 16, A non-transitory computer-readable storage medium configured to store a computer program for a photoelectric conversion device comprising instructions for executing following processes, wherein the photoelectric conversion device includes a plurality of pixels each including a photoelectric conversion unit that emits pulses corresponding to photons, a counter that counts the number of the pulses, and a memory that stores a count value of the counter; the computer program comprising instructions for executing following processes: generating a signal based on a difference between a count value of the counter at the start of an accumulation period and a count value at the end of the accumulation period; performing control so that a signal generated in a first accumulation period is output between the end of the first accumulation period and the end of a second accumulation period, and one full frame period includes the first accumulation period and the second accumulation period longer than the first accumulation period).
Claims 1 – 11 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3 – 6, and 8 - 12 of copending Application No. 18,669,610, Saito et al in view of Numata US Publication No. 2022/0120610. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims in this application are boarder than the claims in Saito et al 18,699,610.
This is a provisional nonstatutory double patenting rejection.
Regarding claim 1 Saito et al discloses of applicant’s A photoelectric conversion device comprising: a plurality of pixels each including: a sensor portion configured to emit a pulse corresponding to an incident photon; a counter configured to count the number of pulses; and a memory configured to store a count value of the counter; one or more memories storing instructions; and one or more processors executing the instructions to generate a signal based on a difference in the count value of the counter between at a start timing and at an end timing of an accumulation period, and output the signal generated in a first accumulation period between an end of the first accumulation period and an end of a second accumulation period, the first accumulation period and the second accumulation period being included in a full frame period, the first accumulation period being shorter than the second accumulation period (claim 1, A photoelectric conversion device comprising: a plurality of pixels each including a sensor unit that emits pulses according to incident photons, and a counter that counts the number of pulses; one or more memories storing instructions; and one or more processors executing the instructions to: generate a signal based on a difference between a count value of the counter at the start of an accumulation period and a count value of the counter at the end of the accumulation period, perform control so that a signal generated during the first accumulation period are output between the end of the first accumulation period and the end of a second accumulation period, the first accumulation period and the second accumulation period being included in a full frame period, and the first accumulation period being shorter than the second accumulation period;
Saito et al discloses photoelectric conversion device with a counter that counts the photo pulses but does not expressively disclose a memory is configured to store a count value of the counter;
Numata teaches a memory storing a count value. Numata teaches of Fig. 1 – 9 of applicant’s a memory is configured to store a count value of the counter (paragraph 0038, FIG. 6 illustrates a clock 600, a timing 601 when the photon is detected by the first counter circuit 211, the count value 602 of the first counter circuit 211 is stored in the memory 214 such that a memory 214 is configured to store a count value 602 of the counter 211). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the circuitry of Saito et al in a manner similar to Numata. Doing so would result improving Saito et al invention in a similar way as Numata – namely the ability to provide a memory storing a count value, in Numata invention, to the photoelectric conversion device with a counter that counts the photo pulses in Saito et al invention.
Regarding claim 2 of the combination of Saito et al in view of Numata, Saito et al further discloses of applicant’s wherein the first accumulation period and the second accumulation period overlap each other (claim 3, wherein the first accumulation period and the second accumulation period overlap each other).
Regarding claim 3 of the combination of Saito et al in view of Numata, Saito et al further discloses of applicant’s wherein the first accumulation period and the second accumulation period start at the same time (claim 4, wherein the first accumulation period and the second accumulation period start at the same time).
Regarding claim 4 of the combination of Saito et al in view of Numata, Saito et al further discloses of applicant’s wherein an end timing of the second accumulation period matches an end timing of the full frame period (claim 5, wherein the end of the second accumulation period matches the end of the full frame period).
Regarding claim 5 of the combination of Saito et al in view of Numata, Saito et al further discloses of applicant’s wherein the one or more processors further execute the instructions to recognize a subject based on at least the signal generated in the first accumulation period (claim 1, one or more memories storing instructions; and one or more processors executing the instructions to: generate a signal and perform control so that a recognition result and a signal generated during the first accumulation period).
Regarding claim 6 of the combination of Saito et al in view of Numata, Saito et al further discloses of applicant’s wherein the one or more processors further execute the instructions to recognize the subject additionally based on the signal generated in the second accumulation period (claim 6, wherein the one or more processors execute the instructions to further recognize the type of the subject based on a signal generated during the second accumulation period).
Regarding claim 7 of the combination of Saito et al in view of Numata, Saito et al further discloses of applicant’s wherein the one or more processors further execute the instructions to display at least the signal generated in the second accumulation period as an image (claim 8, wherein the one or more processors execute the instructions to display at least a signal generated during the second accumulation period as an image).
Regarding claim 8 of the combination of Saito et al in view of Numata, Saito et al further discloses of applicant’s wherein the sensor portion includes an avalanche photodiode (claim 9, wherein the sensor unit is constituted by an avalanche photodiode).
Regarding claim 9 the combination of Saito et al in view of Numata further discloses of applicant’s A movable apparatus comprising: a plurality of pixels each including: a sensor portion configured to emit a pulse corresponding to an incident photon; a counter configured to count the number of pulses; and a memory configured to store a count value of the counter; one or more memories storing instructions; and one or more processors executing the instructions to generate a signal based on a difference in the count value of the counter between at a start timing and at an end timing of an accumulation period, output the signal generated in a first accumulation period between an end of the first accumulation period and an end of a second accumulation period, the first accumulation period and the second accumulation period being included in a full frame period, the first accumulation period being shorter than the second accumulation period, and control an operation of the movable apparatus (Saito et al in claim 10, A movable apparatus comprising and Saito et al in claim 1, a plurality of pixels each including a sensor unit that emits pulses according to incident photons, and a counter that counts the number of pulses; one or more memories storing instructions; and one or more processors executing the instructions to: generate a signal based on a difference between a count value of the counter at the start of an accumulation period and a count value of the counter at the end of the accumulation period, perform control so that a signal generated during the first accumulation period are output between the end of the first accumulation period and the end of a second accumulation period, the first accumulation period and the second accumulation period being included in a full frame period, and the first accumulation period being shorter than the second accumulation period. Numata in paragraph 0015 the information processing apparatus 1000 includes a light receiving lens 1001, a photoelectric conversion device 100, a control unit 1002 that controls the focusing of the light receiving lens 1001 such that control unit 1002 controls a focus operation of the movable apparatus 1000. Numata in paragraph 0038, FIG. 6 illustrates a clock 600, a timing 601 when the photon is detected by the first counter circuit 211, the count value 602 of the first counter circuit 211 is stored in the memory 214 such that a memory 214 is configured to store a count value 602 of the counter 211).
Regarding claim 10 of the combination of Saito et al in view of Numata further discloses of applicant’s A photoelectric conversion method of performing photoelectric conversion in a plurality of pixels each including a sensor portion configured to emit a pulse corresponding to an incident photon, a counter configured to count the number of pulses, and a memory configured to store a count value of the counter, the photoelectric conversion method comprising: generating a signal based on a difference in the count value of the counter between at a start timing and at an end timing of an accumulation period; and outputting the signal generated in a first accumulation period between an end of the first accumulation period and an end of a second accumulation period, the first accumulation period and the second accumulation period being included in a full frame period, the first accumulation period being shorter than the second accumulation period (Saito et al in claim 11, A photoelectric conversion method for performing photoelectric conversion using a plurality of pixels each including a sensor unit that emits pulses according to incident photons, and a counter that counts the number of pulses, the photoelectric conversion method comprising: generating a signal based on a difference between a count value of the counter at the start of an accumulation period and a count value of the counter at the end of the accumulation period; recognizing a type of a subject based on the signal generated during a first accumulation period; and performing control so that a recognition result and a signal generated during the first accumulation period are output between the end of the first accumulation period and the end of a second accumulation period, the first accumulation period and the second accumulation period being included in a full frame period, and the first accumulation period being shorter than the second accumulation period. Numata in paragraph 0038, FIG. 6 illustrates a clock 600, a timing 601 when the photon is detected by the first counter circuit 211, the count value 602 of the first counter circuit 211 is stored in the memory 214 such that a memory 214 is configured to store a count value 602 of the counter 211).
Regarding claim 11 of the combination of Saito et al in view of Numata further discloses of applicant’s A non-transitory computer-readable storage medium configured to store a computer program comprising instructions for executing a photoelectric conversion process of performing photoelectric conversion in a plurality of pixels each including a sensor portion configured to emit a pulse corresponding to an incident photon, a counter configured to count the number of pulses, and a memory configured to store a count value of the counter, the photoelectric conversion process comprising: generating a signal based on a difference in the count value of the counter between at a start timing and at an end timing of an accumulation period; and outputting the signal generated in a first accumulation period between an end of the first accumulation period and an end of a second accumulation period, the first accumulation period and the second accumulation period being included in a full frame period, the first accumulation period being shorter than the second accumulation period (Saito et al in claim 12, A non-transitory computer-readable storage medium configured to store a computer program to control a photoelectric conversion device, the photoelectric conversion device including a plurality of pixels, and each of the pixels including a sensor unit that emits pulses according to incident photons, and a counter that counts the number of pulses, and the program including instructions for executing following processes: generating a signal based on a difference between a count value of the counter at the start of an accumulation period and a count value of the counter at the end of the accumulation period; and outputting a signal generated during the first accumulation period between the end of the first accumulation period and the end of a second accumulation period, the first accumulation period and the second accumulation period being included in a full frame period, and the first accumulation period being shorter than the second accumulation period. Numata in paragraph 0038, FIG. 6 illustrates a clock 600, a timing 601 when the photon is detected by the first counter circuit 211, the count value 602 of the first counter circuit 211 is stored in the memory 214 such that a memory 214 is configured to store a count value 602 of the counter 211).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARK T MONK whose telephone number is (571)270-7454. The examiner can normally be reached Monday thru Friday 8am to 4pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sinh Tran can be reached at 571-272-7564. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MARK T MONK/Primary Examiner, Art Unit 2637