Prosecution Insights
Last updated: October 25, 2026
Application No. 18/669,731

REDUCED LATENCY METADATA ENCRYPTION AND DECRYPTION

Non-Final OA §103
Filed
May 21, 2024
Priority
May 31, 2023 — provisional 63/505,232
Examiner
KANAAN, SIMON P
Art Unit
2407
Tech Center
2400 — Computer Networks
Assignee
Rambus Inc.
OA Round
3 (Non-Final)
83%
Grant Probability
Favorable
3-4
OA Rounds
7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
548 granted / 662 resolved
+24.8% vs TC avg
Strong +16% interview lift
Without
With
+16.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
11 currently pending
Career history
682
Total Applications
across all art units

Statute-Specific Performance

§101
12.5%
-27.5% vs TC avg
§103
41.4%
+1.4% vs TC avg
§102
26.3%
-13.7% vs TC avg
§112
12.3%
-27.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 662 resolved cases

Office Action

§103
DETAILED ACTION Office Action Summary Claims 1-20 are pending in the instant application. Claims 1-20 are rejected under 35 USC § 103. Applicant’s arguments filed 7/6/2026 have been considered but are moot based on new grounds of rejection found upon further search and consideration. Request for Continued Examination A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/6/2023 has been entered. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made. Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Agarwal et al. (US Pre-Grant Publication No: 2017/0006064 A1) hereinafter referred to as Agarwal in view of Pitroda et al. (US Patent No: 4,627,047) hereinafter referred to as Pitroda. As per claims 1, 9 and 17, Agarwal teaches … encrypt or decrypt the first metadata using a first cryptographic algorithm; and (Agarwal, [0074]-[0075], teaches having different algorithms for encryption/decryption) encrypt or decrypt the first data using a second cryptographic algorithm, wherein the first data and the first metadata are stored at a same location, within a memory device, corresponding to a memory address. (Agarwal, [0171], shows data can reside in one or more location) but Agarwal does not teach that the metadata is stored at the same memory-addressable storage location within a memory device; However, Pitroda column 8, lines 64-68 teaches that “random access memory addressable storage locations is comprised of eight cells for storing voice information and at least one cell for storing data information” so multiple pieced of information are stored as the same memory-addressable location of a memory device. It would have been obvious to one having ordinary skill in the art, before the effective filing of the claimed invention to modify the invention of Agarwal with the method of Pitroda, as this is a simple substitution of storing data in same location to storing data at a same memory-addressable location. As per claims 2, 10 and 18, Agarwal in view of Pitroda teaches … wherein the first cryptographic algorithm is a stream cipher, and the second cryptographic algorithm is a block cipher. (Agarwal, [0048] and [0049]) As per claims 3, 11 and 19, Agarwal in view of Pitroda teaches … wherein the cryptographic circuit is further to: receive, from a host, a request to read the first data from a memory device; pre-compute a keystream associated with the first metadata using the memory address; read the first metadata and the first data from the memory device; decrypt the first metadata using the keystream to obtain a decrypted first metadata; decrypt the first data using the second cryptographic algorithm to obtain a decrypted first data; and send the decrypted first data to the host. (Agarwal, [0051]) As per claims 4 and 12, Agarwal in view of Pitroda teaches … wherein the cryptographic circuit is further to determine whether to decrypt a second data based on an indicator within a second metadata. (Agarwal, [0057]) As per claims 5 and 13, Agarwal in view of Pitroda teaches … wherein the cryptographic circuit, responsive to a determination not to decrypt the second data, is further to send a third data to a host, wherein the third data is a pre-defined pattern of data. (Agarwal, [0057]) As per claims 6, 14 and 20, Agarwal teaches … wherein the cryptographic circuit is further to: receive, from a host, a request to write the first data to a memory device; encrypt the first data and the first metadata in parallel to obtain an encrypted first data and an encrypted first metadata; and write the encrypted first data and the encrypted first metadata to the memory device. (Agarwal, [0074]-[0075]) As per claims 7 and 15, Agarwal in view of Pitroda teaches … wherein the cryptographic circuit is further to: receive, from a host, a request to write a second data to a memory device, wherein the second data is a pre-defined pattern of data; obfuscate the second data using a third cryptographic algorithm to obtain obfuscated data; assert an indicator within a second metadata associated with the second data to indicate that the second data is the pre-defined pattern of data; and write the obfuscated data to the memory device. (Agarwal, [0074]-[0075], encrypting portion of data is obfuscating that portion) As per claims 8 and 16, Agarwal in view of Pitroda teaches … wherein a portion of the first data comprises one or more error correcting code (ECC) symbols and the first metadata are encoded within the one or more ECC symbols. (Agarwal, [0048], teaches a digital signature for ensuring correctness) Other Art of Record Guan et al. (US 20240430084 A1) teaches (The disclosure relates to generating a ciphertext of arbitrary and flexibly large size and ensures that an adversary learns little about the encrypted data, even if the decryption key later leaks, unless substantially the entire ciphertext is stored. Given that communication will be inconveniently large for the adversary to store, the incompressible ciphertexts and signatures can be sent and received with low storage requirements for the honest users. In such a setting, the honest users would not store the entire ciphertext or signature, but instead generate, send, and process the communication bit-by-bit in a streaming fashion.) Obokhov (US 20160239666 A1) teaches (A non-deterministic encryption functionality receives and encrypts an open-text input stream. Codes for error-correction are generated for the encrypted stream, and a correctable amount of non-deterministic random error is overlaid onto the encrypted stream and the codes for error-correction. The error-injected encrypted stream and codes for error-correction are re-encrypted and delivered to a using process. A non-deterministic decryption functionality reverses the encryption, in some embodiments using key values used during the encryption, and delivers an open-text stream to a using process. Some embodiments of a non-deterministic encryption include a reversible scrambling layer. In some embodiments, the non-deterministic encryption and decryption functionalities are performed, at least in part, by a controller of a solid state disk. In some embodiments, the functionalities are performed within a secure physical boundary provided by implementation within a single integrated circuit.) De Jong (US 20050069131 A1) teaches (Obfuscation of an application program comprises receiving an obfuscated key decryption program comprising an instruction stream configured to perform a decryption algorithm for a first cryptographic key. The obfuscated key decryption program also has an encrypted second cryptographic key scrambled in its instruction stream. The second cryptographic key is encrypted with the first cryptographic key. The obfuscated key decryption program is executed to decrypt the second cryptographic key. The second cryptographic key is used for decrypting digital content.) Bruno (US 11133924 B2) teaches (Disclosed examples decrypt a first block of sequential blocks using a first decryption key generated based on a first hash of a second decryption key and bit stream data, the first decryption key associated with the first block of the sequential blocks to generate a first segment of a band entropy coded bit stream; generate a third decryption key for a second block of the sequential blocks based on a second hash of the first decryption key and data of the first block of the sequential blocks; decrypt the second block of the sequential blocks using the third decryption key associated with the second block of the sequential blocks to generate a second segment of the band entropy coded bit stream; and merge the first and second segments of the band entropy coded bit stream to generate a source data bit stream using a bit mask for demultiplexing.) Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIMON P KANAAN whose telephone number is (571)270-3906. The examiner can normally be reached on M-F (7AM-4PM). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Catherine Thiaw can be reached on (571) 270-1138. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SIMON P KANAAN/Primary Examiner, Art Unit 2407
Read full office action

Prosecution Timeline

May 21, 2024
Application Filed
Oct 10, 2025
Non-Final Rejection mailed — §103
Jan 09, 2026
Response Filed
May 15, 2026
Final Rejection mailed — §103
Jul 06, 2026
Response after Non-Final Action
Sep 15, 2026
Request for Continued Examination
Sep 24, 2026
Response after Non-Final Action
Oct 01, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
83%
Grant Probability
99%
With Interview (+16.0%)
3y 0m (~7m remaining)
Median Time to Grant
High
PTA Risk
Based on 662 resolved cases by this examiner. Grant probability derived from career allowance rate.

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