DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
The specification recites in paragraph 0007: “In some embodiments, a value of the first count signal during the first time period an exponential power of 2.” Perhaps applicant means “In some embodiments, a value of the first count signal during the first time period is an exponential power of 2”?
The specification recites in paragraph 0017: “In some embodiments, a value of the first count signal during the first time period an exponential power of 2.” Perhaps applicant means “In some embodiments, a value of the first count signal during the first time period is an exponential power of 2”?
Appropriate correction is required.
Claim Objections
Claims 2 and 12 are objected to because of the following informalities:
Regarding claim 2, the claim recites “wherein a value of the first count signal during the first time period an exponential power of 2”. Perhaps applicant means: “wherein a value of the first count signal during the first time period is an exponential power of 2”?
Appropriate correction is required.
Regarding claim 12, the claim recites “wherein a value of the first count signal during the first time period an exponential power of 2”. Perhaps applicant means: “wherein a value of the first count signal during the first time period is an exponential power of 2”?
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-5, 7-11, 14-15 and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2024/0142316) (hereinafter Kim).
Regarding claim 1, Kim teaches a temperature sensor (10) comprising: a clock generating circuit comprising: a bandgap circuit (20) configured to generate a first input signal (Iptat, Ictat) that varies based on a temperature (see paragraphs 0035, 0036); one or more controlled oscillators (30) including a first controlled oscillator configured to receive the first input signal (Iptat, Ictat) and generate a first clock signal (CLKp) (see paragraph 0038); one or more counters including a first counter (CCNT) configured to receive the first clock signal (CLKp) from the clock generating circuit and a first enable signal (RCLK) for a first time period, wherein the first counter (CCNT) is further configured to generate at least a first count signal (TCc, TCp) based at least on the first clock signal (CLKp) and the first enable signal (RCLK) (see Figures 1 and 13-14 and paragraphs 0080-0081); at least one processor (40) and at least one non-transitory memory including computer coded instructions thereon, the computer coded instructions, with the at least one processor, cause the processor to: determine the temperature (Tc) based at least on the first count signal (TCp, TCc); and generate a temperature signal (temperature code) based at least on the temperature, wherein the temperature signal is a binary signal (see Figure 17 and paragraph 0098).
Regarding claim 4, Kim further teaches wherein the first enable signal is based on a reference clock signal (RCLK) (see paragraph 0039).
Regarding claim 5, Kim further teaches a clock divider, and wherein a reference clock signal is provided to the clock divider to generate the first enable signal (RCLK) (see paragraph 0039).
Regarding claim 7, Kim further teaches the first input signal is linearly dependent based on a temperature (see paragraph 0036).
Regarding claim 8, Kim further teaches the first input signal varies proportionally to absolute temperature or varies negatively-proportionally to absolute temperature (see paragraph 0036).
Regarding claim 9, Kim further teaches the bandgap circuit (20) is further configured to generate a second input signal (Ictat) that varies based on the temperature (see paragraph 0036); wherein the one or more controlled oscillators (CCOp, CCOc) include a second controlled oscillator (CCOc) configured to receive the second input signal and generate a second clock signal (CLKc) (see Figures 1 and 13 and paragraph 0039-0042); wherein the one or more counters (TDCp, TDCc) include a second counter (TDCc) configured to receive the second clock signal (CLKc) from the clock generating circuit and the first enable signal (RCLK) (see Figures 1 and 13), wherein the second counter (TDCc) is further configured to generate at least a second count signal (TCc) based at least on the second clock signal (CLKc) and the first enable signal (RCLK) (see Figure 13); and wherein to determine the temperature based at least on the first count signal and the second count signal (TCp, TCc) (see Figures 1 and 13 and paragraphs 0039-0042 and 0062).
Regarding claim 10, Kim further teaches wherein to determine the temperature is further based at least on a gamma signal (γ) and an offset signal (ζ ) (see paragraphs 0147-0149).
Regarding claim 11, Kim teaches a method comprising: generating, with a clock generating circuit, a first clock signal (CLKp), wherein generating the first clock signal (CLKp) comprises: generating, with a bandgap circuit (20), a first input signal (Iptat, Ictat), wherein the first input signal (Iptat, Ictat) varies based on a temperature (see paragraph 0036-0037); receiving the first input signal (Iptat, Ictat) at a first controlled oscillator (30) of one or more controlled oscillators (see Figure 1); generating the first clock signal (CLKp) with the first controlled oscillator based on the first input signal (Iptat, Ictat) (see paragraph 0038); receiving, at a first counter (CCNT) of one or more counters, the first clock signal (CLKp) and a first enable signal (RCLK) for a first time period (see Figures 1 and 13-14 and paragraphs 0080-0081); generating, with the first counter (CCNT), a first count signal (TCp, TCc) based at least on the first clock signal (CLKp, CLKc) and the first enable signal (RCLK); determining the temperature (TC) based at least on the first count signal (TCp, TCc); and generating a temperature signal based at least on the temperature (TC), wherein the temperature signal is a binary signal (see Figure 17 and paragraph 0098).
Regarding claim 14, Kim further teaches wherein the first enable signal is based on a reference clock signal (RCLK) (see paragraph 0039).
Regarding claim 15, Kim further teaches a clock divider, and wherein a reference clock signal is provided to the clock divider to generate the first enable signal based on the reference clock signal (RCLK) (see paragraph 0039).
Regarding claim 17, Kim further teaches the first input signal is linearly dependent based on a temperature (see paragraph 0036).
Regarding claim 18, Kim further teaches the first input signal varies proportionally to absolute temperature or varies negatively-proportionally to absolute temperature (see paragraph 0036).
Regarding claim 19, Kim further teaches comprising: generating, with the clock generating circuit, a second clock signal (CLKc), wherein generating the second clock signal (CLKc) comprises: generating, with the bandgap circuit (20), a second input signal (Ictat), wherein the second input signal (Ictat) varies based on the temperature (see paragraph 0036); receiving the second input signal (Ictat) at a second controlled oscillator (CCOc) of the one or more controlled oscillators (CCOp, CCOc) (see Figures 1 and 13 and paragraph 0039-0042); generating a second clock signal (CLKc) with the second controlled oscillator (CCOc) based on the second input signal (Ictat) (see Figure 13); receiving, at a second counter (TDCc) of one or more counters (TDCp, TDCc), the second clock signal (CLKc) and the first enable signal (RCLK) for a first time period (see Figures 1 and 13 and paragraph 0039-0042); generating, with the second counter (TDCc), a second count signal (TCc) based at least on the second clock signal (CLKc) and the first enable signal (see Figure 13); and wherein determining the temperature is further based at least on the second count signal (TCp, TCc) (see Figures 1 and 13 and paragraphs 0039-0042 and 0062).
Regarding claim 20, Kim further teaches determining the temperature based at least on the first count signal is further based on a gamma signal (γ) and an offset signal (ζ ) (see paragraphs 0147-0149).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-3 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Nakagawa (JP 2011151476 A) (hereinafter Nakagawa).
Regarding claim 2, Kim teaches all the limitations of claim 1.
However, Kim does not explicitly teach wherein a value of the first count signal during the first time period an exponential power of 2.
Nakagawa teaches wherein a value of the first count signal during the first time period an exponential power of 2 (see page 2, lines 15-27).
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to provide the temperature sensor as taught by Kim with a value of the first count signal during the first time period an exponential power of 2 as taught by Nakagawa. One would be motivated to make this combination because by using these techniques, it is possible to configure a data amount monitoring circuit for an asynchronous transfer buffer, in order to keep the desired Hamming distance.
Regarding claim 3, the prior combination teaches all the limitations of claim 2.
However, Kim as modified by Nakagawa does not explicitly teach wherein to determine the temperature based at least on the first count signal the computer coded instructions, with the at least one processor, further cause the processor to perform a binary shift of the first count signal.
Nakagawa teaches wherein to determine the temperature based at least on the first count signal the computer coded instructions, with the at least one processor (data amount monitoring circuit), further cause the processor to perform a binary shift of the first count signal (the binary counter changes from the maximum value to the minimum value) (see page 2, lines 15-27).
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to provide the temperature sensor as taught by the prior combination with a value of the first count signal during the first time period an exponential power of 2 as taught by Nakagawa. One would be motivated to make this combination because by using these techniques, it is possible to configure a data amount monitoring circuit for an asynchronous transfer buffer, in order to keep the desired Hamming distance.
Regarding claim 12, Kim teaches all the limitations of claim 11.
However, Kim does not explicitly teach wherein a value of the first count signal during the first time period an exponential power of 2.
Nakagawa teaches wherein a value of the first count signal during the first time period an exponential power of 2 (see page 2, lines 15-27).
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to provide the temperature sensor as taught by Kim with a value of the first count signal during the first time period an exponential power of 2 as taught by Nakagawa. One would be motivated to make this combination because by using these techniques, it is possible to configure a data amount monitoring circuit for an asynchronous transfer buffer, in order to keep the desired Hamming distance.
Regarding claim 13, the prior combination teaches all the limitations of claim 12.
However, Kim as modified by Nakagawa does not explicitly teach wherein to determine the temperature based at least on the first count signal the computer coded instructions, with the at least one processor, further cause the processor to perform a binary shift of the first count signal.
Nakagawa teaches wherein to determine the temperature based at least on the first count signal the computer coded instructions, with the at least one processor (data amount monitoring circuit), further cause the processor to perform a binary shift of the first count signal (the binary counter changes from the maximum value to the minimum value) (see page 2, lines 15-27).
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to provide the temperature sensor as taught by the prior combination with a value of the first count signal during the first time period an exponential power of 2 as taught by Nakagawa. One would be motivated to make this combination because by using these techniques, it is possible to configure a data amount monitoring circuit for an asynchronous transfer buffer, in order to keep the desired Hamming distance.
Claims 6 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Chauhan (US 9866112) (hereinafter Chauhan).
Regarding claim 6, Kim further teaches the computer coded instructions, with the at least one processor, further cause the processor to generate the first enable signal.
Chauhan teaches the computer coded instructions, with the at least one processor (1012), further cause the processor (via selectable monoshot (202) of processor (1012)) (see Figure 10) to generate the first enable signal (clock input) (106) (see Figures 2, 6 and 10 and column 11, line 34 through column 12, line 45).
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to provide the temperature sensor as taught by Kim with the computer coded instructions, with the at least one processor, further cause the processor to generate the first enable signal as taught by Chauhan. One would be motivated to make this combination for the benefit of providing low power consumption.
Regarding claim 16, Kim teaches all the limitations of claim 11.
However, Kim does not explicitly teach generating, by a processor, the first enable signal, and wherein generating the temperature signal is by the processor.
Chauhan teaches generating, by a processor (via selectable monoshot (202) of processor (1012)) (see Figure 10), the first enable signal (clock input) (106), and wherein generating the temperature signal is by the processor (1012) (see Figures 2, 6 and 10 and column 11, line 34 through column 12, line 45).
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to provide the method as taught by Kim with generating, by a processor, the first enable signal, and wherein generating the temperature signal is by the processor as taught by Chauhan. One would be motivated to make this combination for the benefit of providing low power consumption.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JANICE M SOTO whose telephone number is (571)270-7707. The examiner can normally be reached M-F 8:00am-4:00pm.
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/JANICE M SOTO/ Examiner, Art Unit 2855
/JOHN E BREENE/Supervisory Patent Examiner, Art Unit 2855
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