DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Claims 1-20 are pending and have been examined.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 10 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are:
In reference to claim 10, the claim requires “the thickness of the metal layer is
in a range of from 8 to 12 times the driving power of the integrated circuit chip.” It is unclear what it means for the thickness to be in a range without any units for the thickness or the driving power range, rendering the meaning of claim 10 indefinite.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is that the second substrate contains dielectric material in contact with the front surface (113) of the substrate 10.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1-2, 4-5, 8-11, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20220149004 A1 – hereinafter Kim) in view of von Koblinski et al. (US 20140339694 A1 – hereinafter von Koblinski).
Regarding independent claim 1, Kim teaches:
An integrated circuit package (200 – Fig. 7 – [0075] – “microelectronic
components 700, which can be diced from an underlying wafer, are placed in the cavities 425 to form a reconstituted wafer- and/or panel-level package 200”) , comprising:
a glass substrate (100 – Fig. 3 – [0076] – “glass substrate 100”) comprising a
glass cladding layer (105 – Fig. 3 – [0049] – “glass cladding layer 105”) fused ([0049] – “the layers 105, 107, 110 are fused together”) to a glass core layer (110 – Fig. 3 – [Abstract] – “glass core layer (110)”);
a cavity (425 – Fig. 3 – [0063] – “cavity 425”) formed in the glass substrate (100), the cavity (425) having a floor (310 – Fig. 3 – [0063] – “floor 310 of each of the cavities 425”) defined by the glass core layer (110) and a sidewall (305 – Fig. 3 – [0062] – “sidewalls 305”) defined by the glass cladding layer (105 – Fig. 3 shows this);
a metal layer configured to define a continuous path of thermally and electrically conductive material disposed within the cavity and along a first of the glass cladding layer, the first surface facing opposite an interface between the glass core layer and the glass cladding layer; and
an integrated circuit chip (700 – Fig. 7 – [0073] – “microelectronic components 700 are silicon based IC chips”) disposed within the cavity ([Abstract] – “a microelectronic component (700) disposed in the cavity”) and contacting a portion of the metal layer within the cavity (425).
Kim does not expressly disclose the other limitations of claim 1.
However, in an analogous art, von Koblinski teaches
a metal layer (410 – Fig. 9 – [0079] – “metal layer 410”) configured to define a continuous path of thermally and electrically conductive material ([0079] – “the metal film 410 is formed on all exposed walls and surfaces such as the surface 205a of the first opening 205, the surface 207a of the second opening 207, the surface 206a of the trench 206, the uncovered area of the semiconductor wafer 300, and also on the second side of the glass substrate 200”) disposed within the cavity (205 – Fig. 9 – [0079] – “openings 205”) and along a first surface (Fig. 9 annotated, see below – hereinafter ‘106’) of the glass cladding layer (200 – Fig. 9 – [0078] – “glass substrate 200” – this corresponds to the glass cladding), the first surface (106) facing opposite an interface between the glass core layer (300 – Fig. 9 – [0064] – “permanently bonding the glass substrate 200 to the semiconductor wafer 300, any suitable bonding process can be employed” – this is interpreted as the glass core layer) and the glass cladding layer (200).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the metal layer structure as taught by von Koblinski into Kim.
An ordinary artisan would have been motivated to use the known technique of von Koblinski in the manner set forth above to produce the predictable result of [0002] – “Metal layers are formed on semiconductor materials to provide a good ohmic contact to the semiconductor material and to dissipate heat generated in the semiconductor material during operation of semiconductor devices integrated in the semiconductor material.”
Regarding claim 2, Kim as modified by von Koblinski, teaches claim 1 from which claim 2 depends. Kim does not expressly disclose the limitations of claim 2.
However, in an analogous art, von Koblinski teaches
wherein the metal layer (410) is disposed on an entirety of the sidewall (Fig.
9 annotated, see above – hereinafter ‘SW’) within the cavity (205).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the metal layer structure as taught by von Koblinski into Kim.
An ordinary artisan would have been motivated to use the known technique of von Koblinski in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 4, Kim as modified by von Koblinski, teaches claim 1 from which claim 4 depends. Kim does not expressly disclose the limitations of claim 4.
However, in an analogous art, von Koblinski teaches
wherein the metal layer (410) is disposed on an entirety of the floor (FL).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the metal layer structure as taught by von Koblinski into Kim.
An ordinary artisan would have been motivated to use the known technique of von Koblinski in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 5, Kim as modified by von Koblinski, teaches claim 1 from which claim 5 depends. Kim does not expressly disclose the limitations of claim 5.
However, in an analogous art, von Koblinski teaches
wherein the metal layer (410) is disposed on an entirety of the first surface
(106) of the glass cladding layer (200 – Fig. 9 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the metal layer structure as taught by von Koblinski into Kim.
An ordinary artisan would have been motivated to use the known technique of von Koblinski in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 8, Kim as modified by von Koblinski, teaches claim 1 from which claim 8 depends. Kim does not expressly disclose the limitations of claim 8.
However, in an analogous art, von Koblinski teaches
wherein a thickness of the metal layer (410) is in a range of from about 1
µm to about 20 µm ([0087] – “a metal 401 is deposited by electroplating on regions covered by the metal layer 410. For example, Cu and/or Ni can be plated … The thickness of the plated metal 401 can be between about 10 .mu.m and 150 .mu.m”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the metal layer structure as taught by von Koblinski into Kim.
An ordinary artisan would have been motivated to use the known technique of von Koblinski in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 9, Kim as modified by von Koblinski, teaches claim 1 from which claim 9 depends. Kim does not expressly disclose the limitations of claim 9.
However, in an analogous art, von Koblinski teaches
wherein a thickness of the metal layer (410) is based on a driving power
([0087] – “The thickness of the plated metal 401 can depend on the later function of the metal as a heat sink and electrical contact”) of the integrated circuit chip (310 – [0116] – “The above processes are particularly suitable for flip-chip bonding of the semiconductor device 310”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the metal layer structure as taught by von Koblinski into Kim.
An ordinary artisan would have been motivated to use the known technique of von Koblinski in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 10, Kim as modified by von Koblinski, teaches claim 9 from which claim 10 depends. Kim further teaches
the integrated circuit chip (700).
Kim does not expressly disclose the other limitations of claim 10.
However, in an analogous art, von Koblinski teaches
wherein the thickness ([0106] – “The metal regions 402, 403 can be, for
example at least 10 .mu.m thick and up to 150 .mu.m thick. Furthermore, a lateral electrical insulation even for high-voltage power devices can be reliably provided by the glass substrate 200 which remains between the metal regions 402, 403”) of the metal layer (410) is in a range of from 8 to 12 times the driving power of the integrated circuit chip (610 - [0070]) (kim (700) . Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the metal layer structure as taught by von Koblinski into Kim.
An ordinary artisan would have been motivated to use the known technique of von Koblinski in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 11, Kim as modified by von Koblinski, teaches claim 9 from which claim 11 depends. Kim further teaches
the integrated circuit chip (700).
Kim and von Koblinski do not expressly disclose the other limitations of claim 11.
However, in an analogous art, von Koblinski teaches
wherein the driving power ([0106] – “a lateral electrical insulation even for high-
voltage power devices can be reliably provided by the glass substrate 200 which remains between the metal regions 402, 403”) of the integrated circuit chip is in a range of from about 0.25 W to about 2 W.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the driving power as taught by von Koblinski into Kim.
An ordinary artisan would have been motivated to use the known technique of von Koblinski in the manner set forth above to produce the predictable result as stated above in claim 1.
However, it had been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate that claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex. Parte Masham, 2 USPQ2d 1647 (1987).
Regarding claim 20, Kim as modified by von Koblinski, teaches claim 1 from which claim 20 depends. Kim further teaches
wherein the sidewall (3055) of the cavity (425) is substantially
perpendicular ([0064] – “an angle θ formed between the sidewall 305 and the floor 310 of the cavity 425 (shown in FIG. 3) is 90°”) to the floor (310) of the cavity (425).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of von Koblinski and Kim et al. (US 20210125938 A1 – hereinafter Kim-938).
Regarding claim 3, Kim as modified by von Koblinski, teaches claim 1 from which claim 3 depends. Kim and von Koblinski do not expressly disclose the limitations of claim 3.
However, in an analogous art, Kim-938 teaches
wherein the metal layer (505 – Fig. 10 – [0048] – “shielding layer 505 can have
any suitable composition and be made using any suitable method. Examples of suitable shielding layer compositions include any type of conductive material, including, but not limited to graphene and metals such as titanium, copper, aluminum, nickel, iron, and combinations thereof”) is disposed on a portion of the floor (310 – Fig. 10 annotated, see below – [0041] – “floors 310 of the cavities are defined by the glass core layer 110”).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the metal layer structure as taught by Kim-938 into Kim and von Koblinski.
An ordinary artisan would have been motivated to use the known technique of Kim-938 in the manner set forth above to produce the predictable result of [0006] – “a glass fan-out, the method comprising depositing a shielding layer within a cavity in a glass substrate. The glass substrate includes a glass cladding layer fused to a glass core layer. A silicon chip may be deposited within the cavity.”
Claims 6-7 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of von Koblinski and Elsherbini et al. (US 20210407903 A1 – hereinafter Elsherbini).
Regarding claim 6, Kim as modified by von Koblinski, teaches claim 1 from which claim 6 depends. Kim does not expressly disclose the limitations of claim 6.
However, in an analogous art, von Koblinski teaches
wherein the metal layer (410).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the metal layer structure as taught by von Koblinski into Kim.
An ordinary artisan would have been motivated to use the known technique of von Koblinski in the manner set forth above to produce the predictable result as stated above in claim 1.
Kim and von Koblinski do not expressly disclose the other limitations of claim 6.
However, in an analogous art, Elsherbini teaches
wherein the metal layer comprises a layer of aluminum, a layer of copper, a
layer of graphene, a layer of titanium, or a combination thereof ([0066]) ([0038] – “the supplemental material may be derived from a copper-containing powder, for example. The powder particles may comprise pure copper (e.g., >99% Cu), or comprise a copper composite such as, but not limited to, a copper-graphene composite. Cold spray deposition is capable of depositing compact fused particle metal layers”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the metal layer structure as taught by Elsherbini into Kim and von Koblinski.
An ordinary artisan would have been motivated to use the known technique of Elsherbini in the manner set forth above to produce the predictable result of [0001] – “High-performance integrated circuit (IC) dies such as central and graphics processing units have increasingly larger power demands, prompting new approaches to integrated conductor architectures at package level and circuit board level. Power bottlenecks at package level may be attributed to lateral resistances due to thin traces within package power planes, vertical resistances due to limitations on the size of inter-level vias that interconnect power planes, and contact resistances between socket pins and land grid array pads on the interconnect plane of the package. To address these bottlenecks, wider and/or thicker power-carrying conductors may be fabricated to provide low-resistance paths for power circuits at package and motherboard level.”
Regarding claim 7, Kim as modified by von Koblinski, teaches claim 1 from which claim 7 depends. Kim does not expressly disclose the limitations of claim 7.
However, in an analogous art, von Koblinski teaches
wherein the metal layer (410).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the metal layer structure as taught by von Koblinski into Kim.
An ordinary artisan would have been motivated to use the known technique of von Koblinski in the manner set forth above to produce the predictable result as stated above in claim 1.
However, in an analogous art, Elsherbini teaches
wherein the metal layer comprises a layer of copper and one or more of graphene and carbon ([0038] – “the supplemental material may be derived from a copper-containing powder, for example. The powder particles may comprise pure copper (e.g., >99% Cu), or comprise a copper composite such as, but not limited to, a copper-graphene composite. Cold spray deposition is capable of depositing compact fused particle metal layers”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the metal layer structure as taught by Elsherbini into Kim and von Koblinski.
An ordinary artisan would have been motivated to use the known technique of Elsherbini in the manner set forth above to produce the predictable result as stated above in claim 6.
Regarding claim 12, Kim as modified by von Koblinski, teaches claim 1 from which claim 12 depends. Kim further teaches
the integrated circuit chip (700).
Kim and von Koblinski do not expressly disclose the other limitations of claim 12.
However, in an analogous art, Elsherbini teaches
wherein an operating frequency ([0050] – “the EMI shielding effect depends on
the conductivity of the materials and the electric field frequency. Specifically, at low frequencies, the penetrating depth of the electric field is large, and a thick layer is needed to shield EMI. In contrast, at high frequencies, a thinner layer may be used because the penetrating depth of the electric field is lower. However, since higher frequency shielding is confined near the surface of the conductor, more heat is generated because of surface resistance”) of the integrated circuit chip is equal to or greater than about 28 GHz.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the operating frequency as taught by Elsherbini into Kim and von Koblinski.
An ordinary artisan would have been motivated to use the known technique of Elsherbini in the manner set forth above to produce the predictable result as stated above in claim 6.
However, it had been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate that claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex. Parte Masham, 2 USPQ2d 1647 (1987).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of von Koblinski and Fuergut et al. (US 20100044885 A1 – hereinafter Fuergut).
Regarding claim 13, Kim as modified by von Koblinski, teaches claim 1 from which claim 13 depends. Kim further teaches
the cavity (425).
Kim and von Koblinski do not expressly disclose the other limitations of claim 13.
However, in an analogous art, Fuergut teaches
further comprising an electrically conductive epoxy ([0043] – “the
semiconductor chips 10 are adhesively bonded to the metal layer 20, it is possible to use electrically conductive adhesives which may be based on epoxy resins and be enriched with gold, silver, nickel or copper in order to produce the electrical conductivity”) disposed within the cavity between the integrated circuit chip (10 – Fig. 3C – [0043] – “the semiconductor chips 10 are adhesively bonded to the metal layer 20, it is possible to use electrically conductive adhesives which may be based on epoxy resins and be enriched with gold, silver, nickel or copper in order to produce the electrical conductivity”) and the metal layer (20 – Fig. 3C – [0043] – “the semiconductor chips 10 are adhesively bonded to the metal layer 20, it is possible to use electrically conductive adhesives which may be based on epoxy resins and be enriched with gold, silver, nickel or copper in order to produce the electrical conductivity”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the electrically conductive epoxy structure as taught by Fuergut into Kim and von Koblinski.
An ordinary artisan would have been motivated to use the known technique of Fuergut in the manner set forth above to produce the predictable result of [0043] – “If diffusion soldering is used as a connecting technique, it is possible to use solder materials which lead to intermetallic phases after the end of the soldering operation at the interface between the metal layer 20 and the respective semiconductor chip 10 on account of interface diffusion processes.”
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of von Koblinski, Fuergut, and Kawaguchi (CN 105407624 B).
Regarding claim 14, Kim as modified by von Koblinski and Fuergut, teaches claim 13 from which claim 14 depends. Kim, von Koblinski, and Fuergut do not expressly disclose the limitations of claim 14.
However, in an analogous art, Kawaguchi teaches
wherein one or more of:
the electrically conductive epoxy comprises silver (16 – Fig. – [0233] –
“anisotropic conductive adhesive layer 16 (thickness: 10 μm, silver-plated calcined carbon particles: 5 vol%, surface resistivity: 5 × 10 Ω). This conductive adhesive composition is obtained by mixing an epoxy resin”), and
a thickness of the electrically conductive epoxy (16) is in a range of from
about 3.5 µm to about 13 µm (16 – [0233] – “anisotropic conductive adhesive layer 16 (thickness: 10 μm, silver-plated calcined carbon particles: 5 vol%, surface resistivity: 5 × 10 Ω). This conductive adhesive composition is obtained by mixing an epoxy resin”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the electrically conductive epoxy structure as taught by Kawaguchi into Kim, von Koblinski, and Fuergut.
An ordinary artisan would have been motivated to use the known technique of Kawaguchi in the manner set forth above to produce the predictable result of adhering the a flexible printed circuit board to a metal layer that creates an electrical contact.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of von Koblinski and Mattes et al. (US 20120197155 A1 – hereinafter Mattes).
Regarding claim 15, Kim as modified by von Koblinski, teaches claim 1 from which claim 15 depends. Kim and von Koblinski do not expressly disclose the limitations of claim 15.
However, in an analogous art, Mattes teaches
wherein the integrated circuit chip (140 – Fig. – 4C – [0043] – “die 140 may be
positioned or mounted in the cavity 138”) has a grounding contact (81 – Fig. 4C – [0040] – “ground contact 81”) disposed on a side of the integrated circuit chip (140 – Fig. 4C – [0043] – “die 140 may be positioned or mounted in the cavity 138”) facing the floor (81 – is facing towards the floor of the cavity as shown in Fig. 4C) of the cavity (138 – Fig. – 4C – [0043] – “die 140 may be positioned or mounted in the cavity 138”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the grounding contact structure as taught by Mattes into Kim and von Koblinski.
An ordinary artisan would have been motivated to use the known technique of Mattes in the manner set forth above to produce the predictable result of grounding the device to shield it from outside electrical activity.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of von Koblinski, Mattes, and Wu et al. (US 20240162267 A1 – hereinafter Wu).
Regarding claim 15, Kim as modified by von Koblinski, teaches claim 1 from which claim 16 depends. Kim and von Koblinski do not expressly disclose the limitations of claim 16.
However, in an analogous art, Mattes teaches
further comprising:
a contact (81) disposed on an external surface (Fig. 4C shows this) of the
integrated circuit package (140), the contact (81) thermally and electrically connected to the metal layer (139 – Fig. 4C – [0048] – “metallization connections 139 being formed on the glass substrate 130).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the grounding contact structure as taught by Mattes into Kim and von Koblinski.
An ordinary artisan would have been motivated to use the known technique of Mattes in the manner set forth above to produce the predictable result as stated above in claim 15.
Kim, von Koblinski, and Mattes do not expressly disclose the limitations of claim 16.
However, in an analogous art, Wu teaches
a via (13 – Fig. 13 – [0049] – “via 13”) that extends between the metal layer (15 – Fig. 13 – [0050] – “metal layer 15”) and the contact (9 – Fig. 13 – [0049] – “metal bonding pad 9”), the via (13) thermally and electrically connected (Fig. 13 shows this) to the metal layer (15) and the contact (9),
wherein the contact (9) is disposed proximate to main contacts ([0046] – “image processor and coder 2, a master controller 3, a power supply 4” – these are main component external to the chip and therefore connected by main contacts) of the integrated circuit chip (1 – Fig. 13 – [0046] – “CMOS chip 1”) on the external surface, the main contacts ([0046] – “image processor and coder 2, a master controller 3, a power supply 4” – these are main component external to the chip and therefore connected by main contacts) electrically connected to the integrated circuit chip (1).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the contact and via structure as taught by Wu into Kim, von Koblinski, and Mattes.
An ordinary artisan would have been motivated to use the known technique of Wu in the manner set forth above to produce the predictable result thermally and electrically connecting the device.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of von Koblinski and Huang et al. (US 20050202590 A1 – hereinafter Huang).
Regarding claim 17, Kim as modified by von Koblinski, teaches claim 1 from which claim 17 depends. Kim does not expressly disclose the limitations of claim 17.
However, in an analogous art, von Koblinski teaches
the first surface (106), and the portion of the metal layer (410) disposed along the first surface (106).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the metal layer structure as taught by von Koblinski into Kim.
An ordinary artisan would have been motivated to use the known technique of von Koblinski in the manner set forth above to produce the predictable result as stated above in claim 1.
Kim and von Koblinski do not expressly disclose the other limitations of claim 17.
However, in an analogous art, Huang teaches
further comprising an insulation layer (642 – Fig. 7 – [0005] – “dielectric layer
642” – this is an insulation layer) disposed over the integrated circuit chip (60 – Fig. 7 – [0005] – “chip 60”), the first surface, and the portion of the metal layer disposed along the first surface.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the insulation layer structure as taught by Huang into Kim and von Koblinski.
An ordinary artisan would have been motivated to use the known technique of Huang in the manner set forth above to produce the predictable result [0010] – “to provide a wafer level semiconductor package with a build-up layer, which is free from warpage, crack, and delamination problems and enhances the reliability thereof.”
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of von Koblinski and Lin et al. (US 20090230542 A1 – hereinafter Lin).
Regarding claim 18, Kim as modified by von Koblinski, teaches claim 1 from which claim 18 depends. Kim and von Koblinski do not expressly disclose the limitations of claim 18.
However, in an analogous art, Lin teaches
further comprising a passivation layer (34 – Fig. 2a – [0020] – “passivation
layer 34 is formed over insulating layer 32”) disposed on the insulation layer (32 – Fig. 2a – [0020] – “passivation layer 34 is formed over insulating layer 32”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the insulation and passivation layer structure as taught by Lin into Kim and von Koblinski.
An ordinary artisan would have been motivated to use the known technique of Lin in the manner set forth above to produce the predictable result of [0020] – “A passivation layer 34 is formed over insulating layer 32 for structural support and physical and electrical isolation, and acts as an etching stop layer during etching.”
Regarding claim 19, Kim as modified by von Koblinski and Lin, teaches claim 18 from which claim 19 depends. Kim and von Koblinski do not expressly disclose the limitations of claim 19.
However, in an analogous art, Lin teaches
wherein one or more of insulation layer (32) and the passivation layer (34)
comprises an electrically insulating material, and wherein the electrically insulating material comprises SiO2 ([0020] – “Passivation layer 34 can be made with one or more layers of SixNy, Si3N4, SiN, SiO2”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the insulation and passivation layer structure as taught by Lin into Kim and von Koblinski.
An ordinary artisan would have been motivated to use the known technique of Lin in the manner set forth above to produce the predictable result as stated above in claim 18.
Conclusion
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to GARY ABEL whose telephone number is (571) 272-0246. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm (Eastern).
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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