DETAILED ACTION
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/7/2025 has been entered.
REJECTIONS NOT BASED ON PRIOR ART
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-8 and 17-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites, as amended “wherein at least one of the plurality of second cell blocks is configured to store a first data set for a first cell block of the plurality of first cell blocks and a second data set for the first cell block.” However, the specification recites, with emphasis added:
“each SLC block associated with the SLC block pool 405 may be capable of storing different data sets that are destined for storage in different MLC blocks” (Paragraph 0042);
“each SLC block associated with the SLC block pool 405 may be capable of storing different data sets that are destined for storage in different MLC blocks” (Paragraph 0042);
“the single-level cell block stores multiple data sets, wherein each data set, of the multiple data sets, includes data received from a host device, and wherein two different data sets, of the multiple data sets, are destined for different multi-level cell blocks” (Paragraph 0059);
“each single-level cell block, of the plurality of single-level cell blocks, is capable of storing different data sets that are destined for storage in different multi-level cell blocks of the plurality of multi-level cell blocks;” (Paragraph 0061)
“the single-level cell block stores multiple data sets, wherein each data set, of the multiple data sets, includes data received from a host device, and wherein two different data sets, of the multiple data sets, are destined for different multi-level cell blocks of the plurality of multi-level cell blocks;” (Paragraph 0063).
Therefore, the specification describes the second/SLC cell blocks storing different data sets, where each data set is destined for a different MLC/first block. However, claim 1 recites second/MLC blocks are “configured to store a first data set…and a second data set” for the [same] first cell block. The specification does not adequately describe first and second data sets being for a same first cell block. Therefore, claim 1 contains new matter. Applicant is required to cancel the new matter, or explain how this limitation is described in the specification. Claim 17 is rejected for similar reasons. The dependent claims inherit this rejection.
REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7 and 9-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Agarwal (US 2022/0334747).
Regarding Claim 1, Agarwal teaches a memory device, comprising:
a plurality of first cell blocks (first cell blocks 950 and 952 of Fig. 9), wherein each cell included in the plurality of first cell blocks is capable of storing at least two bits of data (the second partition may be “TLC” blocks which store at least two bits of data, Paragraph 0040, and first cell blocks 950 and 952 are “second partitions,” Paragraph 0076);
a plurality of second cell blocks (cell blocks D0, D1, etc, contained in first partition 902 of Fig. 9 containing “die plane blocks”) configured to store data prior to the data being written to one of the plurality of first cell blocks (“data that is written to the first partition 902 can be immediately moved to an actual zone block in second partitions [zones] (e.g., 950, 952),” Paragraph 0078), wherein each second cell block, of the second plurality of cell blocks, is capable of storing data associated with different first cell blocks of the plurality of first cell blocks (D0 and D1 each store data associated with Zone 0 950, a first cell block, and also zone 1 952, a different first cell block, as shown on Fig. 9);
wherein at least one of the plurality of second cell blocks is configured to store a first data set for a first cell block of the plurality of first cell blocks and a second data set for the first cell block (the first cell block corresponding to Zone 0 950 of Fig. 9, and second cell block D0 stores a first data set for z0/first cell block shown in element 910 of Fig. 9 and another data set for first cell block/z0 shown in element 912 of Fig. 9);
a mapping component configured to store a mapping table that indicates a mapping between a memory location in the plurality of second cell blocks and a corresponding first cell block for which data stored in the memory location is to be migrated using the mapping table (see Fig. 9, where there is mapping between each cell block to a corresponding zone, noted by the arrow to zones 950 and 952 of Fig. 9, the mapping table corresponding to the mapping between the physical cells and the corresponding zone to which the cell belongs, such as Z0 for the top row of data cells in partition 902 of Fig. 9 and the designated second partition 950, and this mapping is used during migration to a new partition at step 1308 of Fig. 13, Paragraph 0102).
Regarding Claim 2, the cited prior art teaches the memory device of claim 1, wherein the plurality of first cell blocks includes multi-level cell blocks that include multi-level cells (the second partition may be “TLC” blocks which store at least two bits of data, Paragraph 0040, and first cell blocks 950 and 952 are “second partitions,” Paragraph 0076).
Regarding Claim 3, the cited prior art teaches the memory device of claim 1, wherein the plurality of second cell blocks includes single-level cell blocks that include single-level cells (element 902 is made of single-level cells, Paragraph 0076).
Regarding Claim 4, the cited prior art teaches the memory device of claim 1, wherein each cell included in the plurality of first cell blocks is capable of storing at least four bits of data (though a TLC area is described at Paragraph 0076, this may be a QLC area, Paragraph 0045).
Regarding Claim 5, the cited prior art teaches the memory device of claim 1, wherein a quantity of the plurality of second cell blocks is less than a quantity of the plurality of first cell blocks (element 902 may be 400 MB, and there may be any number of zones for the first cell blocks 950, 952, and therefore a quantity of the plurality of second cell blocks is less than a quantity of the plurality of first cell blocks, Paragraphs 0072-0076).
Regarding Claim 6, the cited prior art teaches the memory device of claim 1, further comprising one or more components configured to:
write host data, associated with a storage location, to one or more second cell blocks of the plurality of second cell blocks (step 1306 of Fig. 13); and store, in the mapping table, an indication of a mapping between the one or more second cell blocks and a first cell block, of the plurality of first cell blocks, that corresponds to the storage location (the indication corresponding to a logical address stored in a table, Paragraphs 0048-0049, each logical address corresponding to a zone as shown on Fig. 7).
Regarding Claim 7, the cited prior art teaches the memory device of claim 1, further comprising one or more components configured to: identify, using the mapping table, a location, of the plurality of second cell blocks, in which host data is stored (Paragraph 0050); and migrate the host data from the location to a first cell block of the plurality of first cell blocks (step 1308 of Fig. 13).
Regarding Claim 9, Agarwal teaches a memory device, comprising:
a plurality of zones, of a zoned namespace, configured to store data (zones 950 and 952 of Fig. 12, which are part of a zoned namespace, Paragraph 0004);
a plurality of cell blocks (cell blocks D0, D1, etc of first partition 902 of Fig. 9 containing “die plane blocks”) configured to store the data prior to the data being written to one or more zones of the plurality of zones (“data that is written to the first partition 902 can be immediately moved to an actual zone block in second partitions [zones] (e.g., 950, 952),” Paragraph 0078), wherein each cell block, of the plurality of cell blocks, is capable of storing data associated with different zones of the plurality of zones (cell blocks D0-D3 each stores data associated with zone 0 950 and also different zone 1 952, as shown on Fig. 9);
wherein at least one of the plurality of cell blocks is configured to store a first data set for a first zone of the plurality of zones and a second data set for a second zone of the plurality of zones (the first zone corresponding to Zone 0 950 of Fig. 9, and cell block D0 stores a first data set for z0/first zone shown in the first row of element 902 Fig. 9 and a second data set for second cell block/z1 shown in the second row of element 902 of Fig. 9); and
a mapping component configured to store a mapping table that indicates a mapping between a location of the plurality of cell blocks and a corresponding zone, of the plurality of zones, to which data stored at the location is to be migrated using the mapping table (see Fig. 9, where there is mapping between each cell block to a corresponding zone, noted by the arrow to zones 950 and 952 of Fig. 9, the mapping table corresponding to the mapping between the physical cells and the corresponding zone to which the cell belongs, such as Z0 for the top row of data cells in partition 902 of Fig. 9 and the designated second partition 950, and this mapping is used during migration to a new partition at step 1308 of Fig. 13, Paragraph 0102).
Regarding Claim 10, the cited prior art teaches the memory device of claim 9, wherein each zone of the plurality of zones is associated with a respective multi-level cell block of a plurality of multi-level cell blocks of the memory device (multi-level cell blocks 950 and 952 of Fig. 9).
Regarding Claim 11, the cited prior art teaches the memory device of claim 10, wherein each multi-level cell block, of the plurality of multi-level cell blocks, corresponds to a single zone of the plurality of zones (block 950 of Fig. 9 corresponds to zone 0 and block 952 of Fig. 9 corresponds to zone 1).
Regarding Claim 12, the cited prior art teaches the memory device of claim 10, wherein at least two multi-level cell blocks, of the plurality of multi-level cell blocks, correspond to a single zone of the plurality of zones (element 950 of Fig. 9 corresponds to zone 0, and it may be made of multiple/at least two blocks, Paragraph 0034).
Regarding Claim 13, the cited prior art teaches the memory device of claim 10, wherein each multi-level cell included in the plurality of multi-level cell blocks is capable of storing at least two bits of data (“the second partition [of the zone] includes a triple-level cell (TLC) block,” Paragraph 0040).
Regarding Claim 14, the cited prior art teaches the memory device of claim 9, wherein the plurality of cell blocks includes single-level cell blocks (element 902 is made of single-level cells, Paragraph 0076).
Regarding Claim 15, the cited prior art teaches the memory device of claim 9, wherein a quantity of the plurality of cell blocks is less than a quantity of the plurality of zones (the capacity/quantity of the plurality of cell blocks is less than a quantity/capacity of the plurality of zones, Paragraph 0094).
Regarding Claim 16, the cited prior art teaches the memory device of claim 9, further comprising one or more components configured to: receive data and an indication of a zone, of the plurality of zones, associated with storing the data (step 1304 of Fig. 13); write the data to one or more cell blocks of the plurality of cell blocks (step 1306 of Fig. 13); and store, in the mapping table, an indication of a mapping between the one or more cell blocks and the zone (the indication corresponding to a logical address stored in a table, Paragraphs 0048-0049, each logical address corresponding to a zone as shown on Fig. 7).
Regarding Claim 17, Agarwal teaches a memory device, comprising:
a plurality of first cell blocks (first cell blocks 950 and 952 of Fig. 9) each corresponding to a respective zone (block 950 belongs to zone 0 and block belongs to zone 1 as shown Fig. 9) of a zoned namespace (Paragraph 0004), wherein each cell included in the plurality of first cell blocks is capable of storing at least two bits of data (the second partition maybe “TLC” which stores at least two bits of data, Paragraph 0040, and first cell blocks 950 and 952 are “second partitions,” Paragraph 0076);
a plurality of second cell blocks (cell blocks D0, D1, etc, contained in first partition 902 of Fig. 9 containing “die plane blocks”), each capable of storing data associated with different first cell blocks of the plurality of first cell blocks (D0 and D1 each store data associated with Zone 0 950, a first cell block, and also zone 1 952, a different first cell block, as shown on Fig. 9); and
wherein at least one of the plurality of second cell blocks is configured to store a first data set for a first cell block of the plurality of first cell blocks and a second data set for the first cell block (the first cell block corresponding to Zone 0 950 of Fig. 9, and second cell block D0 stores a first data set for z0/first cell block shown in element 910 of Fig. 9 and another data set for first cell block/z0 shown in element 912 of Fig. 9);
one or more components configured to:
store data, in one or more second cell blocks of the plurality of second cell blocks, prior to the data being written to a first cell block of the plurality of first cell blocks (data that is written to the first partition 902 can be immediately moved to an actual zone block in second partitions [zones] (e.g., 950, 952), Paragraph 0078); and store an indication of a mapping between the first cell block and a location of the plurality of second cell blocks to which the data is to be migrated using the mapping (see Fig. 9, where there is mapping between each cell block to a corresponding zone, noted by the arrow to zones 950 and 952 of Fig. 9, the mapping table corresponding to the mapping between the physical cells and the corresponding zone to which the cell belongs, such as Z0 for the top row of data cells in partition 902 of Fig. 9 and the designated second partition 950, and this mapping is used when migrating/transferring data from a first partition to a second partition, step 1308 of Fig. 13, Paragraph 0102 and “the NVM 110 may store a logical-to-physical (L2P) mapping table 120 for the storage device 102 associating each data 119 with a logical address. The L2P mapping table 120 stores the mapping of logical addresses specified for data written from the host device 104 to physical addresses in the NVM 110 indicating the location(s) where each of the data is stored,” Paragraph 0048, see Fig. 2, and note that the “locations” are used – indicating both SLC and TLC data may be stored in the mapping table, and Agarwal indicates the SLC block references are “optional” and may be used for reads, Paragraph 0040, also see step 1310 of Fig. 13, Paragraph 0103).
Regarding Claim 18, the cited prior art teaches the memory device of claim 17, wherein the one or more components are further configured to: migrate the data to the first cell block after a condition is satisfied and using the indication of the mapping (step 1308 of Fig. 13, the condition corresponding to the device being in an idle state and the data is migrated to the zone corresponding to the allocation).
Regarding Claim 19, the cited prior art teaches the memory device of claim 18, wherein the one or more components are further configured to: perform one or more garbage collection operations on the one or more second cell blocks after the data has been migrated to the first cell block (the garbage collection operation corresponding to the erasing of the first partition of Fig. 12, Paragraphs 0094-0095).
Regarding Claim 20, the cited prior art teaches the memory device of claim 17, wherein the plurality of first cell blocks includes multi-level cell blocks that include multi-level cells (“the second partition [of the zone] includes a triple-level cell (TLC) block,” Paragraph 0040).
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Agarwahl in view of Ryu et al (US 2013/0046920).
Regarding Claim 8, the cited prior art teaches the memory device of claim 7, but does not explicitly teach one or more components configured to: determine that the host data is to be migrated to the first cell block based on a size of the host data satisfying a threshold.
Ryu teaches to determine that the host data is to be migrated to the first cell block based on a size of the host data satisfying a threshold (Paragraph 0047).
It would have been obvious to a person having ordinary skill in the art at the time the invention was filed to have implemented the migration of Ryu in the cited prior art in order to make room in faster memory.
ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
Applicant's argument that the cited prior art fails to teach the claims as amended has been considered and is persuasive regarding claims 1-8. Thus, the rejection has been withdrawn. However, the examiner maintains Agarwahl teaches claims 9-20 as amended as described in the rejection above.
RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c).
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. These references include:
Shin et al (US 2021/0263674) teaches MEMORY SYSTEM WITH A ZONED NAMESPACE AND AN OPERATING METHOD THEREOF.
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. ' 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 have been rejected.
DIRECTION OF FUTURE CORRESPONDENCE
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mark Giardino whose telephone number is (571) 270-3565 and can normally be reached on M-F 9:00-5:00- 5:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Jared Rutz can be reached on (571) 272 - 5535. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
/MARK A GIARDINO JR/Primary Examiner, Art Unit 2135