DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/23/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No.12021969. Although the claims at issue are not identical, they are not patentably distinct from each other.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Pub.No.: US 2018/0097618 A1 to Kumar et al(hereafter refenced as Kumar) in view of NPL EP 2 228 941 B1 Encryption Processing apparatus to Nobukata, Hiromi(hereafter referenced as Nobukata),
Regarding claim 1, Kumar discloses “a method comprising: performing, by one or more processing devices, a first set of operations at a first function component, the first set of operations comprising a first portion of a cryptographic operation and a first pre- charge operation” (Embodiments achieve the desired invariance of the charge integrals in that between each two states having a valid logic values (b. bq)=(1,0) or (0,1), a so-called precharge state is inserted, for which both k and kq are charged to the same electrical potential, that is, assume logically invalid values (1. 1) or (0, 0). For the precharge state (1, 1), therefore, a state sequence could be as follows: (1, 1)->(0, 1)->(1, 1)->(1, 0)->(1, 1)->(1,0)->(1, 1)->(0,1) . . . .).
Kumar does not explicitly disclose “and, performing a second set of operations at a second function component, the second set of operations comprising a second portion of the cryptographic operation and a second pre-charge operation, wherein the second portion of the cryptographic operation is performed concurrently with the first pre-charge operation.”
However, Nobukata in an analogous art discloses “and, performing a second set of operations at a second function component, the second set of operations comprising a second portion of the cryptographic operation and a second pre-charge operation, wherein the second portion of the cryptographic operation is performed concurrently with the first pre-charge operation.”(DES operation circuit 100 further includes a first pre-charge control device (P.C. CTL1) 107, a second pre-charge control device (P.C. CTL2) 108, and a second EXOR operation device 109 Nobukata [par.0045]).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Kumar’s cryptographic operation process with Nobukata’s cryptographical process comprising a pre-charge operation in order to provide additional security. One of ordinary skill in the art would have been motivated to combine because Kumar discloses cryptograpraphical process and a precharge state, Nobukata additionally discloses a second precharge operation, and both are from the same field of endeavor.
Regarding claim 2 in view of claim 1, the references combined disclose “wherein the second pre-charge operation is performed at the second function component concurrently with performance of the first portion of the cryptographic operation at the first function component.” (second pre-charge control device (P.C. CTL2) 108, and a second EXOR operation device 109 Nobukata [par.0045]).
Regarding claim 3 in view of claim 1, the references combined disclose “wherein the second portion of the cryptographic operation and the first pre-charge operation are performed during a first clock cycle corresponding to the one or more processing devices” (In any clock cycle , mask circuitry 356 may XOR an output of S - box circuitry 352 with a pseudo - random values generated by PRG circuitry 354 Kumar[par.0049]).
Regarding claim 4 in view of claim 1, the references combined disclose “wherein the second portion of the cryptographic operation is performed using a result of the first portion of the cryptographic operation performed at the first function component” (DES operation circuit 100 further includes a first pre-charge control device (P.C. CTL1) 107, a second pre-charge control device (P.C. CTL2) 108, and a second EXOR operation device 109 Nobukata [par.0045]).
Regarding claim 5 in view of claim 1, the references combined disclose “wherein performing the first set of operations further comprising: storing a result of the first portion of the cryptographic operation performed at the first function component to a memory element associated with the first function component” (memory 502 includes a ROM (read only memory) that stores the programs to be executed by the CPU 501 as well as fixed data for use as operation parameters Nobukata [par.0358]) , “wherein the first pre-charge operation corresponds to a resetting of values stored at the first function component.”(DES operation circuit 100 includes a sixth EXOR operation device 116 and a seventh EXOR operation device 117 serving as a flag resetting device Nobukata [par.0047]).
Regarding claim 6 in view of claim 1, the references combined disclose “further comprising: performing a third set of operations at the first function component, the third set of operations comprising a third portion of the cryptographic operation and a third pre-charge operation, wherein the third portion of the cryptographic operation is performed concurrently with the second pre-charge operation” (third circuitry operable to provide an XOR of a value on the output of the first circuitry and a value on the first output of the second circuitry onto an output of the third circuitry coupled to an input of a fourth circuitry Kumar[par.0116]).
Regarding claim 7 in view of claim 1, the references combined disclose “further comprising: receiving an input data; performing an initial portion of the cryptographic operation at the second function component; and storing an initial result of the initial portion of the cryptographic operation at a memory element associated with the second function component” (memory 502 includes a ROM (read only memory) that stores the programs to be executed by the CPU 501 as well as fixed data for use as operation parameters Nobukata [par.0358]), wherein the first portion of the cryptographic operation of the first set of operations is performed with the initial result” (DES operation circuit 100 further includes a first pre-charge control device (P.C. CTL1) 107, a second pre-charge control device (P.C. CTL2) 108, and a second EXOR operation device 109 Nobukata [par.0045]).
Regarding claim 8, Kumar discloses “a system comprising: a first function component; a second function component; and one or more processing devices operatively coupled to the first function component and the second function component, the one or more processing devices to: perform a first set of operations at the first function component, the first set of operations comprising a first portion of a cryptographic operation and a first pre-charge operation” (Embodiments achieve the desired invariance of the charge integrals in that between each two states having a valid logic values (b. bq)=(1,0) or (0,1), a so-called precharge state is inserted, for which both k and kq are charged to the same electrical potential, that is, assume logically invalid values (1. 1) or (0, 0). For the precharge state (1, 1), therefore, a state sequence could be as follows: (1, 1)->(0, 1)->(1, 1)->(1, 0)->(1, 1)->(1,0)->(1, 1)->(0,1) . . . .).
Kumar does not explicitly disclose “and perform a second set of operations at the second function component, the second set of operations comprising a second portion of the cryptographic operation and a second pre-charge operation, wherein the second portion of the cryptographic operation is performed concurrently with the first pre-charge operation.”
However, Nobukata in an analogous art discloses “and perform a second set of operations at the second function component, the second set of operations comprising a second portion of the cryptographic operation and a second pre-charge operation, wherein the second portion of the cryptographic operation is performed concurrently with the first pre-charge operation.”(DES operation circuit 100 further includes a first pre-charge control device (P.C. CTL1) 107, a second pre-charge control device (P.C. CTL2) 108, and a second EXOR operation device 109 Nobukata [par.0045]).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Kumar’s cryptographic operation process with Nobukata’s cryptographical process comprising a pre-charge operation in order to provide additional security. One of ordinary skill in the art would have been motivated to combine because Kumar discloses cryptograpraphical process and a precharge state, Nobukata additionally discloses a second precharge operation, and both are from the same field of endeavor.
Regarding claim 9 in view of claim 8, the references combined disclose “wherein the second pre-charge operation is performed at the second function component concurrently with performance of the first portion of the cryptographic operation at the first function component” (second pre-charge control device (P.C. CTL2) 108, and a second EXOR operation device 109 Nobukata [par.0045]).
Regarding claim 10 in view of claim 8, the references combined disclose “wherein the second portion of the cryptographic operation and the first pre-charge operation are performed during a first clock cycle corresponding to the one or more processing devices” (In any clock cycle , mask circuitry 356 may XOR an output of S - box circuitry 352 with a pseudo - random values generated by PRG circuitry 354 Kumar[par.0049]).
Regarding claim 11 in view of claim 8, the references combined disclose “wherein the second portion of the cryptographic operation is performed using a result of the first portion of the cryptographic operation performed at the first function component” (DES operation circuit 100 further includes a first pre-charge control device (P.C. CTL1) 107, a second pre-charge control device (P.C. CTL2) 108, and a second EXOR operation device 109 Nobukata [par.0045]).
Regarding claim 12 in view of claim 8, the references combined disclose “wherein to perform the first set of operations the one or more processing devices further to: store a result of the first portion of the cryptographic operation performed at the first function component to a memory element associated with the first function component” (memory 502 includes a ROM (read only memory) that stores the programs to be executed by the CPU 501 as well as fixed data for use as operation parameters Nobukata [par.0358]), “wherein the first pre-charge operation corresponds to a resetting of values stored at the first function component” (DES operation circuit 100 includes a sixth EXOR operation device 116 and a seventh EXOR operation device 117 serving as a flag resetting device Nobukata [par.0047]).
Regarding claim 13 in view of claim 8, the references combined disclose “the one or more processing devices further to: perform a third set of operations at the first function component, the third set of operations comprising a third portion of the cryptographic operation and a third pre-charge operation, wherein the third portion of the cryptographic operation is performed concurrently with the second pre-charge operation” (third circuitry operable to provide an XOR of a value on the output of the first circuitry and a value on the first output of the second circuitry onto an output of the third circuitry coupled to an input of a fourth circuitry Kumar[par.0116]).
Regarding claim 14 in view of claim 8, the references combined disclose (New) The system of claim 8, the one or more processing devices further to:
receive an input data; perform an initial portion of the cryptographic operation at the second function component; and store an initial result of the initial portion of the cryptographic operation at a memory element associated with the second function component” (memory 502 includes a ROM (read only memory) that stores the programs to be executed by the CPU 501 as well as fixed data for use as operation parameters Nobukata [par.0358]),“wherein the first portion of the cryptographic operation of the first set of operations is performed with the initial result.” (DES operation circuit 100 further includes a first pre-charge control device (P.C. CTL1) 107, a second pre-charge control device (P.C. CTL2) 108, and a second EXOR operation device 109 Nobukata [par.0045]).
Regarding claim 15, Kumar discloses “a non-transitory computer-readable storage medium comprising instructions that, when executed by one or more processing devices, cause the one or more processing devices to: perform, by one or more processing devices, a first set of operations at a first function component, the first set of operations comprising a first portion of a cryptographic operation and a first pre-charge operation” (Embodiments achieve the desired invariance of the charge integrals in that between each two states having a valid logic values (b. bq)=(1,0) or (0,1), a so-called precharge state is inserted, for which both k and kq are charged to the same electrical potential, that is, assume logically invalid values (1. 1) or (0, 0). For the precharge state (1, 1), therefore, a state sequence could be as follows: (1, 1)->(0, 1)->(1, 1)->(1, 0)->(1, 1)->(1,0)->(1, 1)->(0,1) . . . .).
Kumar does not explicitly disclose “perform a second set of operations at a second function component, the second set of operations comprising a second portion of the cryptographic operation and a second pre-charge operation, wherein the second portion of the cryptographic operation is performed concurrently with the first pre-charge operation.”
However, Nobukata in an analogous art discloses “perform a second set of operations at a second function component, the second set of operations comprising a second portion of the cryptographic operation and a second pre-charge operation, wherein the second portion of the cryptographic operation is performed concurrently with the first pre-charge operation.”(DES operation circuit 100 further includes a first pre-charge control device (P.C. CTL1) 107, a second pre-charge control device (P.C. CTL2) 108, and a second EXOR operation device 109 Nobukata [par.0045]).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Kumar’s cryptographic operation process with Nobukata’s cryptographical process comprising a pre-charge operation in order to provide additional security. One of ordinary skill in the art would have been motivated to combine because Kumar discloses cryptograpraphical process and a precharge state, Nobukata additionally discloses a second precharge operation, and both are from the same field of endeavor.
Regarding claim 16 in view of claim 15, the references combined disclose “wherein the second pre-charge operation is performed at the second function component concurrently with performance of the first portion of the cryptographic operation at the first function component” (second pre-charge control device (P.C. CTL2) 108, and a second EXOR operation device 109 Nobukata [par.0045]).
Regarding claim 17 in view of claim 15, the references combined disclose “wherein the second portion of the cryptographic operation and the first pre-charge operation are performed during a first clock cycle corresponding to the one or more processing devices”(In any clock cycle , mask circuitry 356 may XOR an output of S - box circuitry 352 with a pseudo - random values generated by PRG circuitry 354 Kumar[par.0049]).
Regarding claim 18 in view of claim 15, the references combined disclose “wherein the second portion of the cryptographic operation is performed using a result of the first portion of the cryptographic operation performed at the first function component” (DES operation circuit 100 further includes a first pre-charge control device (P.C. CTL1) 107, a second pre-charge control device (P.C. CTL2) 108, and a second EXOR operation device 109 Nobukata [par.0045]).
Regarding claim 19 in view of claim 15, the references combined disclose “wherein to perform the first set of operations the one or more processing devices further to: store a result of the first portion of the cryptographic operation performed at the first function component to a memory element associated with the first function component” (memory 502 includes a ROM (read only memory) that stores the programs to be executed by the CPU 501 as well as fixed data for use as operation parameters Nobukata [par.0358]) ,, wherein the first pre-charge operation corresponds to a resetting of values stored at the first function component.” (DES operation circuit 100 includes a sixth EXOR operation device 116 and a seventh EXOR operation device 117 serving as a flag resetting device Nobukata [par.0047]).
Regarding claim 20 in view of claim 15, the references combined disclose “the one or more processing devices further to: perform a third set of operations at the first function component, the third set of operations comprising a third portion of the cryptographic operation and a third pre-charge operation, wherein the third portion of the cryptographic operation is performed concurrently with the second pre-charge operation” (third circuitry operable to provide an XOR of a value on the output of the first circuitry and a value on the first output of the second circuitry onto an output of the third circuitry coupled to an input of a fourth circuitry Kumar[par.0116]).
Conclusion
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/MICHAEL D ANDERSON/Examiner, Art Unit 2433
/JEFFREY C PWU/Supervisory Patent Examiner, Art Unit 2433
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