DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Withdrawn Allowability
The indicated allowability of 1-11, 15 and 19-20 is withdrawn in view of the newly discovered reference(s) to Moon, Jung et al. and Kigo et al. Rejections based on the newly cited reference(s) follow.
Claim Objections
Claims 19 and 20 are objected to because of the following informalities:
With respect to claim 19, the recitation of “a first unidirectional current path” in line 2-3 should be changed to -- the first unidirectional current path --.
With respect to claim 20, the recitation of “a first unidirectional current path” in line 3 should be changed to -- the first unidirectional current path --.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Moon (USPAPN 2006/0221000).
With respect to claim 1, Moon discloses, in Figs. 2-4, an apparatus (one of Figs. 3 operational details disclosed in Figs. 2 and 4) comprising:
a switch (SW1) , a first diode (D1), and a first inductance (L2) coupled in series (above are serially connected) between a first node (N1) and a second node (node connected to Cs1);
a second diode (D2) and a second inductance (L3) coupled in series (above serially connected) between the first node (N1) and the second node (node connected to Cs1); and
a third inductance (L1) coupled between the first node (N1) and a third node (N2).
With respect to claim 2, the apparatus of claim 1, wherein the first diode is arranged to enable current to flow from the second node to the first node when the switch is closed (when SW1 is closed the circuit operates as claimed, see SW1 and IL1 of Fig. 2 and a/b of Fig. 4).
With respect to claim 3, the apparatus of claim 2, wherein the second diode is arranged to enable current to flow from the first node to the second node (when SW2 is enabled the circuit operates as claimed and c/d of Fig. 4).
With respect to claim 4, the apparatus of claim 1, wherein each of the first inductance, the second inductance, and the third inductance comprises at least one inductor (L2, L3 and L1 each comprise at least one inductor).
Claim(s) 8-11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jung et al. (USPN 7,768,477).
With respect to claim 8, Jung et al. discloses, in Figs., 7 and 8, an apparatus (Fig. 7 operational details disclosed in Fig. 8) to produce a waveform (output wave form to the panel capacitor see wave for the reaches V2 of Fig. 8), the apparatus comprising:
a switch (Q1) and a first diode (D1) arranged in series (serially connected) and coupled between a first node (Cs node) and a second node (node connected to the anode of D3), and responsive to the switch being closed (connected as claimed when Q1 is closed), a pulse is initiated at a third node (pulse of current provided by Q1, D1 and L1/D3 to the panel when Q1 is closed, note output rises as Q1 is closed in Fig. 8); and
a power supply (70 supplying stored power of C1/Vr to the third node when Q5 is closed) arranged to provide a voltage between the second node and the third node (voltage between the second node as coupled to the second node via C1 to the output/cathode of D2 when Q5 is closed, see Fig. 8) while a ramped voltage is produced (while the output is being ramped up to V2 while Q5 is closed see T2 to T3) after the pulse at the third node (Q5 is continued to be closed after Q1 is open, i.e., the pulse of Q1 is stopped, and the third node is continued to be ramped up to V2 by Q5 and L3).
With respect to claim 9, the apparatus of claim 8, comprising a first inductance in series with the switch and the first diode (L1).
With respect to claim 10, the apparatus of claim 9, wherein the first inductance comprises at least one inductor (L1 is an inductor).
With respect to claim 11, the apparatus of claim 9, comprising a second inductance (L2) and a second diode (D2) arranged in series and coupled between the second node (connected to the second node via the anode to cathode connection of D3) and the first node (to Cs via Q2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5, 15 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moon (USPAPN 2006/0221000).
With respect to claim 5, Moon merely discloses a single one of the first, second and third inductance, a the switch being a single switch and the first and second diodes being single diodes. Thus, Moon fails to disclose “wherein one or more of the first inductance, the second inductance, and the third inductance comprises a plurality of inductors the switch comprises a plurality of switches arranged in series, and one or both of the first diode and the second diode comprises a plurality of diodes”.
However, it is old and well-known to connect multiple inductors in either series, parallel, or a combination of parallel and serially connected inductors for the purpose of, among other things, setting an overall effective inductance of the combined inductors (i.e., serially connected inductors increase the total effective inductance and parallel connected inductors decrease the total effective inductance).
Furthermore, it old and well-known to replace a single switch transistor (such as the switch of Moon) with multiple serially-connected-cascode switch transistors for the purpose of, among other things, providing a higher gain device.
Additionally, it is old and well-known to replace a single diode with multiple serially connected diodes (such as the single diodes of Moon) for the purpose of, among other things, increasing the breakdown voltage of the combined diodes as well as the switching threshold of the combined diode device.
Examiner takes official notice of the above well-known replacements of the above single devices with multiple devices for reasons discussed above.
It would have been obvious to replace the single inductors of Moon with multiple inductors connected in series and/or parallel, replace the single switch transistors of Moon with multiple cascode connected switch transistors and replace the single diodes with multiple serially connected diodes, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. One would have been motivated to do so for the purpose of, among other things, setting an overall effective inductance of the combined inductors, providing a higher gain transistor switch device, and , increasing the breakdown voltage of the combined diodes as well as the switching threshold of the diodes.
With respect to claim 15, Moon discloses, a method for producing a waveform, the method (method of operating Fig. 3) comprising:
providing a first unidirectional current pathway between a first node and a second node (one the paths from first node Cs1 to N2 via D1, D1, L2 and L or via SW2, D2, L3 and L1) ;
providing a second unidirectional current pathway between the first node and the second node (other one the paths from first node Cs1 to N2 via D1, D1, L2 and L or via SW2, D2, L3 and L1) ;
providing a voltage to the second node (SW3 providing VS to N2); and
closing and opening the first unidirectional current pathway to produce pulses of the waveform at a third node (pulses produced by the closing of one of SW1 and SW2 to produce the waveform Vcp of Fig. 4).
Moon ostensibly repeatedly performs the above switching (i.e., opening and closes of one of SW1 and SW2) when the circuit generates the Vcp pulse more than once. However, Moon only discloses a single operation of the circuit/generation of Vcp in Fig. 4. Nevertheless it would have been obvious to one of ordinary skill in the art to generate more than a single pulse of Vcp for the purpose of, among other things, being able to change the voltage multiple times. As receive proper value/use of the circuitry, since a single use driver circuit would be wasteful and of little use.
With respect to claim 19, the method of claim 15, wherein providing the first unidirectional current pathway comprises arranging a first diode to provide a first unidirectional current path from the second node to the first node (D2 operates as claimed when SW2 is closed), and wherein providing the second unidirectional current pathway comprises arranging a second diode to provide a second unidirectional current path from the first node to the second node (D1 operates as claimed when SW1 is closed).
With respect to claim 20, the method of claim 19, wherein providing the first unidirectional current pathway comprises arranging a first diode in series with a first inductance to provide a first unidirectional current path from the second node to the first node (D2 with L3 when SW2 is closed), and wherein providing the second unidirectional current pathway comprises arranging a second diode in series with a second inductance to provide a second unidirectional current path from the first node to the second node (D1 with L2 when SW1 is closed)..
Claim(s) 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moon (USPAPN 2006/0221000) in view of Kigo et al. (USPN 7,050,022).
Moon discloses a power supply (recovery power supply/voltage stored within Cs1; or alternatively the GND power supply) coupled to the second node (i.e., node of Cs1 not connected to GND; alternatively GND coupled to the second node via Cs1). Moon fails to disclose an additional inductor between Cs1 and N2. Thus, Moon fails to disclose, “a power supply and a fourth inductance coupled in series between the second node and the third node”.
However, Kigo et al., in Fig. 27, discloses adding an additional switch (Q6) diode (D4) and inductor (L1) connected between a power supply (Cr, or ground via Cr, i.e., effectively equivalent to Cs1 of Moon) and an output node (N1, i.e., effectively equivalent to N2 of Moon) of a sustain driver (i.e., circuit similar to 52 of Moon).
The additional switch, diode and inductor allows for decreases losses in the sustain driver, see to Col. 26 lien 58 to Col. 27 line 6 of Kigo et al.
It would have been obvious to add the additional switch additional switch (Q6) diode (D4) and inductor (L1) of Kigo et al. between Cs1 and N2 of Moon for the purpose of decreasing the losses in the sustain driver of Moon.
With respect to claim 7, Moon discloses, the apparatus of claim 6 comprising a controller (device controlling SW1, SW2, SW3 and S4) to open and close the switch to produce (the switches are opened and closed), at the third node (N2), voltage pulses (Vcp pulsed up at a and/or b of Fig. 4 of Moon) and a ramped voltage between the voltage pulses (Vcp ramped down at d and/c of Fig. 4 of Moon).
Moon ostensibly repeatedly performs the above switching when the circuit generates the Vcp pulse more than once. However, Moon only discloses a single operation of the circuit/generation of Vcp in Fig. 4. Nevertheless it would have been obvious to one of ordinary skill in the art to generate more than a single pulse of Vcp for the purpose of, among other things, being able to change the voltage multiple times. As receive proper value/use of the circuitry, since a single use driver circuit would be wasteful and of little use.
.
Allowable Subject Matter
Claims 12-14 and 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/THOMAS J. HILTUNEN/Primary Examiner, Art Unit 2849