DETAILED ACTION
Claims 1 – 20 are cancelled.
Claims 21 – 40 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-31, 33-40 are rejected under 35 U.S.C. 103 as being unpatentable over Flajslik et al (US 20190097935 A1), in view of Zhao et al (US 20110078482 A1).
Regarding claim 21, Flajslik discloses a method, comprising:
translating, by a compiler, a program into a scheduled series of operations to be
performed by at least a first processor and a second processor [0035: The expected performance data may be hard coded, read from a configuration file, received from an administrator compute device, or obtained from another source] [Fig. 1, node switch 160, processor 204 and 0023: the port logic 212 may be embodied as part of a system-on-a-chip (SoC) that includes one or more processors] [0019: the processor 204 may be embodied as a single or multi-core processor(s)];
determining, by the compiler, an expected flit transmission count for executing the scheduled series of operations on the first processor and the second processor [0035: the node switch 160 may obtain expected traffic rate data indicative of a number of units of data expected to be transferred through the node switch 160 over a predefined time period (e.g., each second)][Fig. 4];
comparing the expected flit transmission count to an actual flit transmission count generated during execution of the scheduled series of operations on the first processor and the second processor [0036: the node switch 160 may obtain measured traffic rate data indicative of a number of units of data transferred through the node switch 160 over a time period (e.g., per second), as indicated in block 422]; and
performing subsequent operations in response to determining whether the measured performance satisfied the expected performance.
However, Flajslik does not disclose modifying a clock speed of at least one of the first processor or the second processor based on the comparison of the expected flit transmission count to the actual flit transmission count.
Zhao discloses modifying a clock speed of at least one of the first processor or the second processor based on the comparison of the expected flit transmission count to the actual flit transmission count [abstract: a number of input and output audio samples measured over a predetermined sample period. In one embodiment, a sample difference may be determined by subtracting the measured number of input audio samples from the measured number of output audio samples. This sample difference may then be compared to a predetermined threshold. When the absolute value of the sample difference is greater than the predetermined threshold, the output clock rate may be adjusted either upwards or downwards][0035-0037].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Flajslik and Zhao together because they both directed to determine the difference between the expected communication information with the actual communication information. Morotomi’s teaching of adjusting the clock based on the sample difference may be determined by subtracting the measured number of input audio samples from the measured number of output audio samples would allow Flajslik to compensate for deviations between expected and actual data transfer between expected and actual data transfer behavior and thereby maintain communication timing synchronization.
Regarding claim 22, Flajslik and Zhao disclose the method of claim 21, wherein modifying the clock speed of the at least one of the first processor or the second processor based on the comparison of the expected flit transmission count to the actual flit transmission count comprises: determining that the actual flit transmission count is less than the expected flit transmission count; and in response to determining that the actual flit transmission count is less than the expected flit transmission count, lengthening one or more clock periods of the at least one of the first processor or the second processor [Flajslik: 0035-0036][Zhao, abstract 0035-0037].
Regarding claim 23, Flajslik and Zhao disclose the method of claim 21, wherein modifying the clock speed of the at least one of the first processor or the second processor based on the comparison of the expected flit transmission count to the actual flit transmission count comprises: determining that the actual flit transmission count is greater than the expected flit transmission count; and in response to determining that the actual flit transmission count is less than the expected flit transmission count, shortening one or more clock periods of the at least one of the first processor or the second processor [Flajslik: 0035-0036][Zhao, abstract 0035-0037].
Regarding claim 24, Flajslik discloses the method of claim 21, wherein the expected flit transmission count and the actual flit transmission count provide respective counts of a plurality of flits, wherein a flit of the plurality of flits represents a smallest unit of data that is transferrable in a network architecture comprising the first processor and the second processor [Flajslik: 0035-0036].
Regarding claim 25, Flajslik discloses the method of claim 21, further comprising:
executing a global notify event for at least the first processor and the second processor;
and in response to the global notify event, resetting the actual flit transmission count [Flajslik: 0035-0036].
Regarding claim 26, Flajslik discloses the method of claim 21, wherein the expected flit transmission count and the actual flit transmission count are defined for a first chip-to-chip (C2C) link between the first processor and the second processor [Flajslik: 0019,0023, 0035].
Regarding claim 27, Flajslik discloses the method of claim 26, wherein the first processor comprises a second C2C link between the first processor and a third processor [Flajslik: 0019,0023, 0035].
Regarding claim 28, Flajslik discloses the method of claim 27, wherein the first processor, the second processor, and the third processor comprise a network topology comprising a minimum spanning tree, wherein the first processor comprises a parent node of the minimum spanning tree, and wherein the second processor and the third processor comprise child nodes of the minimum spanning tree [Flajslik: 0019,0023, 0035].
Regarding claim 29, Flajslik discloses the method of claim 28, wherein at least one of the second processor or the third processor comprise a leaf node of the minimum spanning tree, the leaf node defining no C2C links to child processors of the at least one of the second processor or the third processor [Flajslik: 0019,0023, 0035].
Regarding claim 30, Flajslik and Zhao disclose the method of claim 21, wherein modifying the clock speed of the at least one of the first processor or the second processor based on the comparison of the expected flit transmission count to the actual flit transmission count comprises: determining a difference between the expected flit transmission count and the actual flit transmission count; generating a clock adjustment value based on the difference between the expected flit transmission count and the actual flit transmission count; and applying the clock adjustment value to the clock speed of the at least one of the first processor or the second processor [Flajslik: 0035-0036][Zhao, abstract 0035-0037].
Regarding claim 31, Flajslik and Zhao disclose the method of claim 30, wherein generating the clock adjustment value is based on a look-up table (LUT) that defines the clock adjustment value as output when the difference between the expected flit transmission count and the actual flit transmission count is provided as input [Flajslik: 0035-0036][Zhao, abstract 0035-0037].
Regarding claim 33, Flajslik and Zhao disclose the method of claim 21, wherein the scheduled series of operations translated by the compiler comprises status indicators respective to at least some of the scheduled series of operations, the status indicators indicating whether a clock period associated with a respective operation is eligible to be shortened or lengthened [Flajslik: 0035-0036][Zhao, abstract 0035-0037].
Regarding claim 34, Flajslik and Zhao disclose the method of claim 21, wherein the clock speed of the at least one of the first processor or the second processor comprises a high-frequency clock phase period (HFCPP) of a phase-locked loop (PLL) associated with the at least one of the first processor or the second processor [Flajslik: 0035-0036][Zhao, abstract 0035-0037].
Regarding claims 35- 39, these claims are rejected for the same reasons as set forth in claims 21-23,25,30, respectively.
Regarding claim 40, this claim is rejected for the same reasons as set forth in claim 21.
Allowable Subject Matter
Claim 32 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior arts of record do not disclose nor suggest the limitation recited in claim 32.
Response to Arguments
Applicant’s arguments filed on 07/21/2026 have been fully considered but are moot in view of new ground(s) of rejection because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Examiner's note: Examiner has cited particular paragraphs and columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner (see MPEP § 2123).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHIL K NGUYEN whose telephone number is (571)270-3356. The examiner can normally be reached 9:30 a.m - 5 p.m.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at (571)270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PHIL K NGUYEN/Primary Examiner, Art Unit 2176
