DETAILED ACTION
Claims 1 – 17 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1,4,5,11,14 and 15 are objected to because of the following informalities:
In each of the claim recite “patent”. It should be “parent” instead.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claims 16 and 17 recite “the chip clock” lacks of antecedence basis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-15 are rejected under 35 U.S.C. 103 as being unpatentable over Morotomi (US Publication US 20150156524 A1) and in view of Krause (US Publication US 20030195983 A1).
Regarding claim 1, Morotomi discloses an electronic system for a plurality of devices in a parent-child network, comprising:
a digital counter circuit for counting packets received by a child device in the network from a parent device [0040: the receiving buffer control unit 230 sends the MPEG-2 TTS packets to a counter value comparison unit 242 as packets having flag information every predetermined number of packets (for example, every 32 packets)] [0041-0042][0063] [0065-0066]; and
a process for synchronizing the clocks of the parent and child devices by a) comparing counts of packets that are sent and received by the parent device and the child device, and b) increasing or decreasing the speed of the clock of the child device depending on the difference in the counts of the number of packets received by the child device, and the number of packets sent by the parent device [0040-0042][0065-0067][0066: Then the counter value comparison unit 242 carries out the clock adjustment process for the transmission clock generation unit 241 (step S209). Specifically, if the count value between flags of the received packets is greater than the count value of the clock generated by the VCXO, the counter value comparison unit 242 increases the frequency of the transmission clock generation unit 241 in accordance with the magnitude of the difference…Alternatively, if the count value between flags of the received packets is less than the count value of the clock generated by the VCXO, the counter value comparison unit 242 reduces the frequency of the transmission clock generation unit 241 in accordance with the magnitude of the difference].
However, Morotomi does not disclose: (1) the parent and child devices are processor devices and (2) flits (a unit of data).
Krause discloses (1) the parent and child devices are processor devices and (2) flits (a unit of data) [Figs. 3-4, communicating flits between network processors] [0121: When a frame is placed onto a link, the frame is further broken down into flits] [0127-0133].
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Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Morotomi and Krause together because they both directed to communicate data between network devices. Krause’s disclosing communicate flits between network processors would allow Morotomi to utilize the teachings to other devices such as network processors and also to increase the efficiency by packetizing the communication message into flits.
Regarding claim 2, Morotomi and Krause disclose the electronic system of claim 1, where the expected number of flits sent by the parent processor is calculated at the time when software to be executed on the child processor is compiled [Morotomi, 0040,0063-0066: expected number of packets sent and received] [Krause, Figs 3-4, 0121, 0127-0133: flits between processors].
Regarding claim 3, Morotomi and Krause disclose the electronic system of claim 1, where the clocks of the parent and child processors are indicated to be aligned if the difference in the counts of the numbers of flits sent and received are approximately zero (Morotomi, [0040-0042][0065-0066][0067: the discrepancy generated between the expected receiving interval (clock) between flags in the packets and the VCXO clock]) ([Krause, Figs 3-4, 0121, 0127-0133: flits between processors]).
Regarding claim 4, Morotomi and Krause disclose the electronic system of claim 1, where if the counter and comparison indicates that fewer flits are received than expected, then the child processor clock lengthens on or more of its clock periods relative to the clock of the patent processor (Morotomi, [0065-0066][0067: the discrepancy generated between the expected receiving interval (clock) between flags in the packets and the VCXO clock])(Krause, Figs 3-4, 0121, 0127-0133: flits between processors).
Regarding claim 5, Morotomi and Krause disclose the electronic system of claim 1, where if the counter and comparison indicates that more flits are received than expected, then the child processor clock shortens on or more of its clock periods relative to the clock of the patent processor (Morotomi, [0065-0066][0067: the discrepancy generated between the expected receiving interval (clock) between flags in the packets and the VCXO clock])(Krause, Figs 3-4, 0121, 0127-0133: flits between processors).
Regarding claim 6, Morotomi and Krause disclose the system of claim 1, wherein the flits are flow control units [0121-0133: Flits are the smallest unit of flow control in the network].
Regarding claim 7, Morotomi and Krause disclose the system of claim 1, wherein the flits are flow control digits [0121-0133: Flits are the smallest unit of flow control in the network].
Regarding claim 8, Morotomi and Krause disclose the system of claim 1, wherein each flit represents a fraction of a packet [0121: When a frame is placed onto a link, the frame is further broken down into flits][0122-0133].
Regarding claim 9, Morotomi and Krause disclose the system of claim 1, wherein each flit carries a few bits of information [0143-0144: bits].
Regarding claim 10, Morotomi and Krause disclose the system of claim 1, wherein each flit carries a few bytes of information [0143-0144].
Regarding claims 11-15, these claims are directed to the method claims for implementing the steps of the system claims 1-5. Thus, they are rejected for the same reasons as set forth in claims 1-5 above.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Morotomi (US Publication US 20150156524 A1) and in view of Krause (US Publication US 20030195983 A1) and in further view of Guim Bernat (US 20230029026 A1).
Regarding claim 16, Morotomi and Krause disclose the chip clock sets a rate of reception of flits from a parent processor, wherein the parent is one of a processor or a FPGA device [0065-0066] [0067: the discrepancy generated between the expected receiving interval (clock) between flags in the packets and the VCXO clock])(Krause, Figs 3-4, 0121, 0127-0133: flits between processors). However, they do not disclose wherein the chip clock is a Tensor Streaming Processor chip clock and
Guim Bernat discloses wherein the chip clock is a Tensor Streaming Processor chip clock [0059: each host device (e.g., 515a-n) may include respective local or attached memory (e.g., 605a-c) as well respective processing hardware 610a-c (e.g., CPU, FPGA, GPU, tensor processing unit (TPU), accelerator hardware, etc.)].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Morotomi, Krause and Guim Bernat together because they directed to communicate data between network devices. Guim Bernat’s disclosing of the chip clock is a Tensor Streaming Processor chip clock would allow Morotomi in view of Krause to increase the efficiency by utilizing the type of processor such as tensor processor.
Regarding claim 17, Guim Bernat discloses the system of claim 11 wherein the chip clock is a Tensor Streaming Processor chip clock and the chip clock sets a rate of reception of flits from a parent processor, wherein the parent is one of a processor or a FPGA device [0059: each host device (e.g., 515a-n) may include respective local or attached memory (e.g., 605a-c) as well respective processing hardware 610a-c (e.g., CPU, FPGA, GPU, tensor processing unit (TPU), accelerator hardware, etc.)].
Conclusion
Examiner's note: Examiner has cited particular paragraphs and columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner (see MPEP § 2123).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHIL K NGUYEN whose telephone number is (571)270-3356. The examiner can normally be reached 9:30 a.m - 5 p.m.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at (571)270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PHIL K NGUYEN/Primary Examiner, Art Unit 2176
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