Prosecution Insights
Last updated: April 19, 2026
Application No. 18/670,300

PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING PRINTED WIRING BOARD

Non-Final OA §103
Filed
May 21, 2024
Examiner
LEE, PETE T
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Ibiden Co. Ltd.
OA Round
1 (Non-Final)
75%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
85%
With Interview

Examiner Intelligence

Grants 75% — above average
75%
Career Allow Rate
578 granted / 773 resolved
+6.8% vs TC avg
Moderate +10% lift
Without
With
+10.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
33 currently pending
Career history
806
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
56.8%
+16.8% vs TC avg
§102
26.0%
-14.0% vs TC avg
§112
12.2%
-27.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 773 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Election/Restriction Applicant’s election without traverse of claims 1-10 in the reply filed on 02/24/2026 is acknowledged. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim (s) 1-3, 5, 7, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Komatsu et al. (US 2020/0219794 A1) hereinafter Komatsu in view of Idomoto et al. (WO 2007000855 A1) hereinafter Idomoto. Regarding claim 1, Komatsu discloses, in Fig.1, a printed wiring board (5), comprising: an insulating layer (1); and a conductor layer (202) formed on the insulating layer and having a plurality of degas holes (see 220 in Fig.3) formed such that the degas holes are penetrating through the conductor layer (202) and exposing a plurality of portions of the insulating layer (1) wherein the conductor layer is formed such that the degas holes have polygon shape (see square shape in Fig.3). Komatsu is silent with respect to wherein the conductor layer is formed such that each of the degas holes is a polygon shape having at least one inner angle of 100 degrees or more. Idomoto discloses holes (Fig.1; [0052]; page 5) with is a polygon shape having at least one inner angle of 100 degrees or more (see octagon shape in [0052] where the inner angle is 135). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the shape as shown by Idomoto to modify the shape of the degas holes in order to increase the allowed density of the holes to form more circuit connections in a compact area to perform more various circuit operations. Regarding claim 2, Komatsu discloses wherein the conductor layer is formed such that the polygon shape of each of the degas holes is an approximate parallelogram (see square shape in Fig.3). Regarding claim 3, a modified Komatsu discloses wherein the conductor layer is formed such that the polygon shape of each of the degas holes is an approximate regular octagon (see octagon shape in [0052] where the inner angle is 135). Regarding claim 5, Komatsu discloses wherein the conductor layer comprises a metal plating film (202 is a copper plating film). Regarding claim 7, Komatsu discloses, wherein the insulating layer (1) comprises resin (1; [0044]). Regarding claim 9, Komatsu fails to specifically discloses wherein the conductor layer is formed such that the plurality of degas holes is formed at a pitch in a range of 5 µm to 50 µm. It would have been obvious to one of ordinary skill in the art at the time the invention was made to use a pitch in a range of 5 µm to 50 µm in order to ensure proper thermal heat dissipation for the holes, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ233. Claim (s) 4 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Komatsu in view of Idomoto, as applied claim 1, and further in view of Chen et al. (US 2023/0299034 A1) hereinafter Chen. Regarding claim 4, a modified Komatsu fails to specifically disclose wherein the conductor layer includes a plurality of wirings and at least one of a power layer and a ground layer. Chen discloses wherein the conductor layer includes a plurality of wirings and at least one of a power layer and a ground layer ([0017]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Chen to modify the conductor layer of Komatsu in order to perform circuit functions. Regarding claim 6, Komatsu discloses wherein the conductor layer comprises a metal plating film (202 is a copper plating film). Claim (s) 8 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Komatsu in view of Idomoto, as applied claim 1, and further in view of Ishiguro et al. (US 2019/0394877 A1) hereinafter Ishiguro. Regarding claim 8, a modified Komatsu fails to specifically disclose wherein the insulating layer comprises resin and inorganic particles. Ishiguro discloses wherein the insulating layer comprises resin (1401; Fig.1A) and inorganic particles ([0048]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Ishiguro to modify the resin of Komatsu in order to enhance thermal stability. Regarding claim 10, a modified Komatsu fails to specifically disclose a core substrate such that the insulating layer is formed on the core substrate. Ishiguro discloses a core substrate (30; Fig.1A) such that the insulating layer (1401) is formed on the core substrate (see Fig.1A). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of claimed invention to use the teachings of Ishiguro to modify the resin of Komatsu in order to perform various circuit operations. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETE LEE whose telephone number is (571) 270-5921. The examiner can normally be reached on Monday-Friday (2nd & 4th Friday Off). If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Timothy Dole can be reached at (571) 272-2229 The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /PETE T LEE/Primary Examiner, Art Unit 2848
Read full office action

Prosecution Timeline

May 21, 2024
Application Filed
Mar 07, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604418
PRINTED CIRCUIT BOARD ASSEMBLY FOR AN AIRCRAFT SOLID STATE POWER CONTROLLER
2y 5m to grant Granted Apr 14, 2026
Patent 12604399
SUBSTRATE FOR PRINTED WIRING BOARD AND PRINTED WIRING BOARD
2y 5m to grant Granted Apr 14, 2026
Patent 12603196
HYBRID SUPERCONDUCTING CABLE
2y 5m to grant Granted Apr 14, 2026
Patent 12598695
HALF-BRIDGE SWITCH ARRANGEMENT
2y 5m to grant Granted Apr 07, 2026
Patent 12592337
CAPACITOR AND ELECTRONIC DEVICE COMPRISING SAME
2y 5m to grant Granted Mar 31, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
75%
Grant Probability
85%
With Interview (+10.5%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 773 resolved cases by this examiner. Grant probability derived from career allow rate.

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