DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 10/06/2025 have been fully considered but they are not persuasive.
Regarding Applicant’s arguments that Koizumi in view of Tsai does not teach the limitation “a multiplexer configured to: receive the clock signal and the intermediate clock signal” of claim 1, the Examiner respectfully disagrees.
Koizumi discloses a memory circuit (See Koizumi: Figure 5, Memory circuit 140-0 and 210a) that includes phase lock loop (PLL) timing circuits (Fig. 5, PLL 151 and 152; i.e. timing circuit of claim 1) that generates a write and read clock (Fig. 5, Read clock 152 and write clock 151; i.e. a clock signal having a first frequency and an intermediate clock signal having a second frequency, respectively, of claim 1) and further includes a switching circuit (Fig. 5, Switch 163; i.e. multiplexer of claim 1) that receives a first read enable signal (Fig. 5, Switching circuit 163 receives a read enable signal 158) and a second read enable signal (Fig. 5, Switching circuit 163 receives read enable signal 157). Koizumi further discloses that the first read enable signal 158 is synchronized with the first clock (Read clock is clock signal having first frequency of claim 1; Paragraph 0057, the second REn transmission circuit 158, and the second timer 162 operate on the read clock) and the second read enable signal 157 is synchronized by the intermediate clock (Write clock is intermediate clock having second frequency of claim 1; Paragraph 0057, the first REn transmission circuit 157, and the first timer 161 operate on the write clock).
While Applicant argues that the first read enable signal and the second read enable signals are not the clock with the first frequency and the intermediate clock with the second frequency and instead are only synchronized with the first frequency clock and intermediate clock, the read enable signals being synchronized with the read and write clocks means that the read enable signals are operating using the clock frequency and therefore can be defined as read enable signals including clocks. Thus, the first read enable signal 158 includes the read clock (i.e. clock with first frequency of claim 1) and the second read enable 157 includes the write clock (i.e. intermediate clock with second frequency of claim 1) because they are both synchronized with the clocks. The claims make no mention of the switching circuit receiving only the first and intermediate clock signals nor does the claim state that the clock signals do not include read enable signals. Furthermore, the section Citation of Pertinent Prior Art below in the Office Action includes references (i.e. Okuno, Chang, Batra) that indicate that a read enable signal is commonly referred to as a clock signal.
Regarding Applicant’s arguments that Koizumi in view of Tsai does not teach the limitation “a modulator configured to adjust a pulse width of the internal clock signal” of claim 7, the Examiner respectfully disagrees.
The primary reference Koizumi discloses generating a read clock and write clock (i.e. read clock is first clock of claim 7 and write clock is internal clock of claim 7) using phase locked loop circuits (PLLs), however Koizumi does not disclose that the pulse width of the internal clock is adjusted, thus the secondary reference Tsai was incorporated to disclose adjusting the duty cycle and frequency of the clock signal (See Tsai: Fig. 2, Modulator 210 adjusts width of read clock RC1 to generate write clock WC; Paragraph 0005, duty cycle adjusting circuit is configured for performing duty cycle adjustment on one of the plurality of reference clock signals according to a duty cycle detection signal to generate an output clock signal having a duty cycle… Paragraph 0045, divides a frequency of the read clock signal RC1 to generate a frequency-divided signal FRS).
While Applicant argues that no mention of pulse width is present in the secondary reference Tsai, the duty cycle is directly related to the pulse width (See formula in Citation of Pertinent Prior Art below where Duty cycle = Pulse Width divided by Period T; i.e. D = PW/T) thus by adjusting the duty cycle to divide a clock frequency, the width of the duty cycle has to be increased/decreased which is the same as changing the size of a pulse width (e.g. increasing/decreasing the duty cycle directly correlates with increasing/decreasing the pulse width). Furthermore, the section Citation of Pertinent Prior Art below in the Office Action includes references (i.e. Mayell, Li, Mann) that state that adjusting the duty cycle is well-known to be the same as adjusting a pulse width.
See Detailed Rejection Below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7-9, and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Koizumi (US 2022/0189520) in view of Tsai (US 2024/0135999).
Regarding claim 1, Koizumi teaches a memory circuit (Fig. 5, Memory circuit includes NAND controller 140-0 and memory chip 210a), comprising: a timing circuit (Fig. 5, Timing circuits 151 and 152 are phase lock loop circuits (PLL) that generate clock timing; Paragraph 0045, NAND controller 140-0 includes a write PLL (WPLL) 151 and a read PLL (RPLL) 152) including: a clock signal having a first frequency and output an intermediate clock signal having a second frequency (Fig. 5, Write clock 151 and read clock 152; Paragraph 0045, WPLL 151 generates a clock used in, for example, data transfer in the write operation. The RPLL 152 generates a clock used in, for example, data transfer in the read operation) having a second frequency that is smaller than the first frequency (Fig. 5, Write clock (i.e. second frequency) is smaller than read clock (i.e. first frequency); Paragraph 0045, The read clock may be set to a higher frequency than the write clock); a multiplexer configured to: receive the clock signal and the intermediate clock signal (Fig. 5, Switching circuit 163 (i.e. mux) receives first clock via 158 and second clock via 157; Paragraph 0057, first REn transmission circuit 157, and the first timer 161 operate on the write clock… second REn transmission circuit 158, and the second timer 162 operate on the read clock); receive a selection signal indicating a selection of the clock signal or the intermediate clock signal (Fig. 5, Switch 163 receives command 153 to switch between clocks 157 and 158; Paragraph 0092, NAND command sequence control circuit 153 causes the switching circuit 163 to switch the transmission circuit to transmit the read enable signal REn from the second REn transmission circuit 158 to the first REn transmission circuit 157); and output one of the clock signal or the intermediate clock signal based on the selection signal (Fig. 5, First clock via circuit 158 and second clock via 157 is output from switching circuit 163; Paragraph 0063, switching circuit 163 switches a transmission circuit between the first REn transmission circuit 157 and the second REn transmission circuit 158); and a memory controller (Fig. 1, Memory controller 100 includes NAND controller 140 of Figure 5) configured to be: read via a first interface synchronized to the clock signal at the first frequency (Fig. 5, Read interface 160/156 is synchronized with read clock; Paragraph 0048, In the read operation the NAND controller 140-0 transfers, to the memory chip 210a, the read enable signal REn synchronized with the read clock… Paragraph 0075, read data, acquired by the DQ/DQS reception circuit 156, is transmitted via the read data path 160); and programmed via a second interface synchronized to the intermediate clock signal at the second frequency (Fig. 5, Write interface 159/155 (i.e. programming data into memory) is synchronized with write clock; Paragraph 0046, In the write operation, the NAND controller 140-0 transfers, to the memory chip 210a, the data strobe signal DQS synchronized with the write clock… Paragraph 0067, write data) is transmitted to the DQ/DQS transmission circuit 155 via the write data path 159).
Koizumi does not teach the memory circuit comprising the timing circuit including: a flip-flop configured to receive a clock signal having a first frequency and output an intermediate clock signal having a second frequency that is a fraction of the first frequency.
Tsai teaches the memory circuit (Fig. 2, Circuit) comprising the timing circuit (Fig. 2, Timing circuit 120) including: a flip-flop configured to receive a clock signal having a first frequency (Fig. 2, Flip flop 214 receives RC1 (Read clock 1)) and output an intermediate clock signal having a second frequency that is a fraction of the first frequency (Fig. 2, Frequency divider 215 divides (i.e. make a fraction of) the read clock (i.e. first frequency) into FRS (i.e. second frequency); Paragraph 0045, divide-by-2 frequency division circuit 215 (abbreviated as FFD in FIG. 2) divides a frequency of the read clock signal RC1 to generate a frequency-divided signal FRS).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Koizumi’s memory circuit to incorporate the teachings of Tsai and include a flip-flop frequency divider to switch between outputting the divided clock signal or original clock signal to the multiplexer.
One of ordinary skill in the art would be motivated to make the modifications in order to efficiently create compatibility and provide support for a heterogeneous range of memory device types that utilize different speeds and signal calibrations (See Tsai: Paragraph 0003).
Regarding claim 2, Koizumi in view of Tsai teaches the memory circuit of claim 1.
Tsai teaches the memory circuit comprising wherein the flip-flop is a divide-by-two-counter (Fig. 2, Flip-flop circuit system 210 divides signal by two; Paragraph 0051, Under such a condition, the write clock signal WC is generated to have a frequency half of that of the read clock signal RC1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Koizumi’s memory circuit to incorporate the teachings of Tsai and include a flip-flop frequency divider to output the divided clock signal or original clock signal to the multiplexer.
One of ordinary skill in the art would be motivated to make the modifications in order to efficiently create compatibility and provide support for a heterogeneous range of memory device types that utilize different speeds and signal calibrations (See Tsai: Paragraph 0003).
Regarding claim 3, Koizumi in view of Tsai teaches the memory circuit of claim 1.
Tsai teaches the memory circuit comprising wherein the second frequency is half of the first frequency (Fig. 2, Flip-flop circuit system 210 divides signal by two; Paragraph 0051, Under such a condition, the write clock signal WC is generated to have a frequency half of that of the read clock signal RC1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Koizumi’s memory circuit to incorporate the teachings of Tsai and include a flip-flop frequency divider to output the divided clock signal or original clock signal to the multiplexer.
One of ordinary skill in the art would be motivated to make the modifications in order to efficiently create compatibility and provide support for a heterogeneous range of memory device types that utilize different speeds and signal calibrations (See Tsai: Paragraph 0003).
Regarding claim 4, Koizumi in view of Tsai teaches the memory circuit of claim 1. Koizumi teaches the memory circuit comprising wherein the memory controller includes one or more of one time programmable memory, flash memory, solid state memory, magnetic memory, field programmable gate array (FPGA), programmable logic array (PLA), random access memory (RAM), read only memory (ROM) (Fig. 1, Memory controller 100 includes RAM 130).
Regarding claim 7, Koizumi teaches a memory circuit (Fig. 5, Memory circuit), comprising: a timing circuit (Fig. 5, Timing circuits 151 and 152) configured to generate an internal clock signal having an internal clock frequency (Fig. 5, Write clock 151 and read clock 152; Paragraph 0045, WPLL 151 generates a clock used in, for example, data transfer in the write operation. The RPLL 152 generates a clock used in, for example, data transfer in the read operation); a modulator configured to generate a first clock signal having a first frequency, wherein the first frequency is smaller than the internal clock frequency (Paragraph 0045, The read clock may be set to a higher frequency than the write clock); and a memory controller (Fig. 1, Memory controller 100 includes NAND controller 140 of Figure 5) configured to be: read via a first interface synchronized to the internal clock signal at the internal clock frequency (Fig. 5, Read interface 160/156 is synchronized with read clock; Paragraph 0048, In the read operation the NAND controller 140-0 transfers, to the memory chip 210a, the read enable signal REn synchronized with the read clock, that is, the clock generated by the RPLL 152); and programmed via a second interface synchronized to the first clock signal at the first frequency (Fig. 5, Write interface 159/155 (i.e. programming data into memory) is synchronized with write clock; Paragraph 0046, In the write operation, the NAND controller 140-0 transfers, to the memory chip 210a, the data strobe signal DQS synchronized with the write clock, that is, the clock generated by the WPLL 151).
Koizumi does not teach the memory circuit comprising a modulator configured to adjust a pulse width of the internal clock signal to generate a first clock signal having a first frequency, wherein the first frequency is a fraction of the internal clock frequency.
Tsai teaches the memory circuit comprising a modulator configured to adjust a pulse width of the internal clock signal to generate a first clock signal having a first frequency (Fig. 2, Modulator 210 adjusts width of read clock RC1 to generate write clock WC; Paragraph 0045, divides a frequency of the read clock signal RC1 to generate a frequency-divided signal FRS), wherein the first frequency is a fraction of the internal clock frequency (Fig. 2, Frequency divider 215 divides read clock (i.e. first frequency) into FRS (i.e. second frequency); Paragraph 0045, divide-by-2 frequency division circuit 215 (abbreviated as FFD in FIG. 2) divides a frequency of the read clock signal RC1 to generate a frequency-divided signal FRS).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Koizumi’s memory circuit to incorporate the teachings of Tsai and include a flip-flop frequency divider to output the divided clock signal or original clock signal to the multiplexer.
One of ordinary skill in the art would be motivated to make the modifications in order to efficiently create compatibility and provide support for a heterogeneous range of memory device types that utilize different speeds and signal calibrations (See Tsai: Paragraph 0003).
Regarding claim 8, Koizumi in view of Tsai teaches the memory circuit of claim 7.
Tsai teaches the memory circuit comprising wherein the first frequency is half of the internal clock frequency (Fig. 2, Modulator 120 divides signal by two; Paragraph 0051, Under such a condition, the write clock signal WC is generated to have a frequency half of that of the read clock signal RC1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Koizumi’s memory circuit to incorporate the teachings of Tsai and include a flip-flop frequency divider to output the divided clock signal or original clock signal to the multiplexer.
One of ordinary skill in the art would be motivated to make the modifications in order to efficiently create compatibility and provide support for a heterogeneous range of memory device types that utilize different speeds and signal calibrations (See Tsai: Paragraph 0003).
Regarding claim 9, Koizumi in view of Tsai teaches the memory circuit of claim 7. Koizumi teaches the memory circuit comprising wherein the memory controller includes one or more of one time programmable memory, flash memory, solid state memory, magnetic memory, field programmable gate array (FPGA), programmable logic array (PLA), random access memory (RAM), read only memory (ROM) (Fig. 1, Memory controller 100 includes RAM 130).
Regarding claim 12, Koizumi teaches a method of operating a memory controller (Fig. 1, Memory controller 100 includes NAND controller 140), comprising: generating a clock signal having a first frequency (Fig. 5, Write clock 151 and read clock 152; Paragraph 0045, WPLL 151 generates a clock used in, for example, data transfer in the write operation. The RPLL 152 generates a clock used in, for example, data transfer in the read operation); generating a second clock having a second frequency, wherein the second frequency is smaller than the first frequency (Paragraph 0045, The read clock may be set to a higher frequency than the write clock); and reading memory of the memory controller (Fig. 1, Memory controller 100 is coupled to a memory 200) via a first interface synchronized to the clock signal at the first frequency (Fig. 5, Read interface 160/156 is synchronized with read clock; Paragraph 0048, In the read operation the NAND controller 140-0 transfers, to the memory chip 210a, the read enable signal REn synchronized with the read clock, that is, the clock generated by the RPLL 152); or programming via a second interface synchronized to the intermediate clock signal at the second frequency (Fig. 5, Write interface 159/155 (i.e. programming data into memory) is synchronized with write clock; Paragraph 0046, In the write operation, the NAND controller 140-0 transfers, to the memory chip 210a, the data strobe signal DQS synchronized with the write clock, that is, the clock generated by the WPLL 151).
Koizumi does not teach the method comprising generating a second clock signal having a second frequency, wherein the second frequency is a fraction of the first frequency.
Tsai teaches the method comprising generating a second clock signal having a second frequency, wherein the second frequency is a fraction of the first frequency (Fig. 2, Frequency divider 215 divides read clock (i.e. first frequency) into FRS (i.e. second frequency); Paragraph 0045, divide-by-2 frequency division circuit 215 (abbreviated as FFD in FIG. 2) divides a frequency of the read clock signal RC1 to generate a frequency-divided signal FRS).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Koizumi’s method to incorporate the teachings of Tsai and include a flip-flop frequency divider to output the divided clock signal or original clock signal to the multiplexer.
One of ordinary skill in the art would be motivated to make the modifications in order to efficiently create compatibility and provide support for a heterogeneous range of memory device types that utilize different speeds and signal calibrations (See Tsai: Paragraph 0003).
Regarding claim 13, Koizumi in view of Tsai teaches the method of claim 12.
Tsai teaches the method comprising wherein generating the second clock signal comprises generating the second clock signal using a flip-flop including a divide-by-two counter (Fig. 2, Flip-flop circuit system 210 divides signal by two; Paragraph 0051, Under such a condition, the write clock signal WC is generated to have a frequency half of that of the read clock signal RC1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Koizumi’s method to incorporate the teachings of Tsai and include a flip-flop frequency divider to output the divided clock signal or original clock signal to the multiplexer.
One of ordinary skill in the art would be motivated to make the modifications in order to efficiently create compatibility and provide support for a heterogeneous range of memory device types that utilize different speeds and signal calibrations (See Tsai: Paragraph 0003).
Regarding claim 14, Koizumi in view of Tsai teaches the method of claim 12.
Tsai teaches the method comprising wherein the second frequency is half of the first frequency (Fig. 2, Flip-flop circuit system 210 divides signal by two; Paragraph 0051, Under such a condition, the write clock signal WC is generated to have a frequency half of that of the read clock signal RC1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Koizumi’s method to incorporate the teachings of Tsai and include a flip-flop frequency divider to output the divided clock signal or original clock signal to the multiplexer.
One of ordinary skill in the art would be motivated to make the modifications in order to efficiently create compatibility and provide support for a heterogeneous range of memory device types that utilize different speeds and signal calibrations (See Tsai: Paragraph 0003).
Regarding claim 15, Koizumi in view of Tsai teaches the method of claim 12. Koizumi teaches the method comprising wherein the memory is one or more of one time programmable memory, flash memory, solid state memory, magnetic memory, field programmable gate array (FPGA), programmable logic array (PLA), random access memory (RAM), read only memory (ROM) (Fig. 1, Memory controller 100 coupled to NAND memory 200).
Claims 5-6, 10-11, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Koizumi (US 2022/0189520) in view of Tsai (US 2024/0135999) and further in view of Kim (US 2020/0089299).
Regarding claim 5, Koizumi in view of Tsai teaches the memory circuit of claim 1. Koizumi teaches the memory circuit comprising the memory controller (Fig. 1, 100).
Neither Koizumi nor Tsai teaches the memory circuit comprising wherein the memory controller comprises one or more of an Advanced eXtensible Interface (AXI) or an Advanced Peripheral Bus (APB) interface.
Kim teaches the memory circuit comprising wherein the memory controller comprises one or more of an Advanced eXtensible Interface (AXI) or an Advanced Peripheral Bus (APB) interface (Fig. 16, Processor 700 includes APB/AXI; Paragraph 0172, bus type of AMBA protocol includes Advanced High-performance Bus (AHB), Advanced Peripheral Bus (APB), Advanced eXtensible Interface (AXI)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Koizumi/Tsai’s memory circuit to incorporate the teachings of Kim and include AXI and APB interface protocols in the controller of Koizumi.
One of ordinary skill in the art would be motivated to make the modifications in order to implement an SoC design via on-chip protocols, thus improving form factor, reducing power dissipation, and enabling industrial manufacturing (See Kim: Paragraph 0172).
Regarding claim 6, the combination of Koizumi/Tsai/Kim teaches the memory circuit of claim 5. Koizumi teaches the memory circuit comprises wherein the first interface is the first frequency and the second interface is the second frequency (Paragraph 0045, The read clock may be set to a higher frequency than the write clock).
Kim teaches the memory circuit comprises wherein the AXI configured to operate at 125 megahertz (MHz) and the APB interface configured to operate at 62.5 MHz (Fig. 3C, Any number of frequency dividers/multipliers can be used to configure clock frequencies; Paragraph 0070, clock modulation circuit 120b may include any number of frequency dividers and any number of multipliers… Paragraph 00172, bus type of AMBA protocol includes Advanced High-performance Bus (AHB), Advanced Peripheral Bus (APB), Advanced eXtensible Interface (AXI)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Koizumi/Tsai’s memory circuit to incorporate the teachings of Kim and include AXI and APB interface protocols in the controller of Koizumi that uses 125 MHz frequency and 62.5 MHz frequency.
One of ordinary skill in the art would be motivated to make the modifications because Koizumi discloses that any frequency can be used (See Koizumi: Paragraph 0045), and thus it would have been obvious to make the combination in order to implement an SoC design via on-chip protocols, thus improving form factor, reducing power dissipation, and enabling industrial manufacturing (See Kim: Paragraph 0172) while also being able to adapt with future design specifications.
Regarding claim 10, Koizumi in view of Tsai teaches the memory circuit of claim 7. Koizumi teaches the memory circuit comprising the memory controller (Fig. 1, 100).
Neither Koizumi nor Tsai teaches the memory circuit comprising wherein the memory controller comprises one or more of an Advanced eXtensible Interface (AXI) or an Advanced Peripheral Bus (APB) interface.
Kim teaches the memory circuit comprising wherein the memory controller comprises one or more of an Advanced eXtensible Interface (AXI) or an Advanced Peripheral Bus (APB) interface (Fig. 16, Processor 700 includes APB/AXI; Paragraph 0172, bus type of AMBA protocol includes Advanced High-performance Bus (AHB), Advanced Peripheral Bus (APB), Advanced eXtensible Interface (AXI)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Koizumi/Tsai’s memory circuit to incorporate the teachings of Kim and include AXI and APB interface protocols in the controller of Koizumi.
One of ordinary skill in the art would be motivated to make the modifications in order to implement an SoC design via on-chip protocols, thus improving form factor, reducing power dissipation, and enabling industrial manufacturing (See Kim: Paragraph 0172).
Regarding claim 11, the combination of Koizumi/Tsai/Kim teaches the memory circuit of claim 10. Koizumi teaches the memory circuit comprises wherein the first interface is the internal frequency and the second interface is the first frequency (Paragraph 0045, The read clock may be set to a higher frequency than the write clock).
Kim teaches the memory circuit comprises wherein the AXI configured to operate at 125 megahertz (MHz) and the APB interface configured to operate at 62.5 MHz (Fig. 3C, Any number of frequency dividers/multipliers can be used to configure clock frequencies; Paragraph 0070, clock modulation circuit 120b may include any number of frequency dividers and any number of multipliers… Paragraph 00172, bus type of AMBA protocol includes Advanced High-performance Bus (AHB), Advanced Peripheral Bus (APB), Advanced eXtensible Interface (AXI)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Koizumi/Tsai’s memory circuit to incorporate the teachings of Kim and include AXI and APB interface protocols in the controller of Koizumi that uses 125 MHz frequency and 62.5 MHz frequency.
One of ordinary skill in the art would be motivated to make the modifications because Koizumi discloses that any frequency can be used (See Koizumi: Paragraph 0045), and thus it would have been obvious to make the combination in order to implement an SoC design via on-chip protocols, thus improving form factor, reducing power dissipation, and enabling industrial manufacturing (See Kim: Paragraph 0172) while also being able to adapt with future design specifications.
Regarding claim 16, Koizumi in view of Tsai teaches the method of claim 12. Koizumi teaches the method comprising the memory controller (Fig. 1, 100).
Neither Koizumi nor Tsai teaches the method comprising wherein the memory controller comprises one or more of an Advanced eXtensible Interface (AXI) or an Advanced Peripheral Bus (APB) interface.
Kim teaches the memory circuit comprising wherein the memory controller comprises one or more of an Advanced eXtensible Interface (AXI) or an Advanced Peripheral Bus (APB) interface (Fig. 16, Processor 700 includes APB/AXI; Paragraph 0172, bus type of AMBA protocol includes Advanced High-performance Bus (AHB), Advanced Peripheral Bus (APB), Advanced eXtensible Interface (AXI)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Koizumi/Tsai’s method to incorporate the teachings of Kim and include AXI and APB interface protocols in the controller of Koizumi.
One of ordinary skill in the art would be motivated to make the modifications in order to implement an SoC design via on-chip protocols, thus improving form factor, reducing power dissipation, and enabling industrial manufacturing (See Kim: Paragraph 0172).
Regarding claim 17, the combination of Koizumi/Tsai/Kim teaches the method of claim 16. Koizumi teaches the method comprises wherein the first interface is the first frequency and the second interface is the second frequency (Paragraph 0045, The read clock may be set to a higher frequency than the write clock).
Kim teaches the method comprises wherein the AXI configured to operate at 125 megahertz (MHz) and the APB interface configured to operate at 62.5 MHz (Fig. 3C, Any number of frequency dividers/multipliers can be used to configure clock frequencies; Paragraph 0070, clock modulation circuit 120b may include any number of frequency dividers and any number of multipliers… Paragraph 00172, bus type of AMBA protocol includes Advanced High-performance Bus (AHB), Advanced Peripheral Bus (APB), Advanced eXtensible Interface (AXI)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Koizumi/Tsai’s method to incorporate the teachings of Kim and include AXI and APB interface protocols in the controller of Koizumi that uses 125 MHz frequency and 62.5 MHz frequency.
One of ordinary skill in the art would be motivated to make the modifications because Koizumi discloses that any frequency can be used (See Koizumi: Paragraph 0045), and thus it would have been obvious to make the combination in order to implement an SoC design via on-chip protocols, thus improving form factor, reducing power dissipation, and enabling industrial manufacturing (See Kim: Paragraph 0172) while also being able to adapt with future design specifications.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US PGPUB 2016/0351269 to Okuno discloses that a read enable signal is referred to as a clock signal (See Okuno: Paragraph 0052, The read enable signal (clock signal) REn input from the outside is supplied to the frequency division circuit 33 and the multiplexer 32).
US PGPUB 2015/0160688 to Chang discloses that a read enable signal synchronized to a clock is called a read-enable clock signal (See Chang: Figure 1, RE# and Paragraph 0029, the read-enable clock signal RE#).
US PGPUB 2018/0136851 to Batra discloses that the read enable signal is called the read enable clock signal (See Batra: Paragraphs 0099, The contacts 550 also include contacts 550 for true and complementary signals for a read enable clock RE).
US PGPUB 2020/0195124 to Mayell discloses that adjusting a duty cycle is referred to as pulse width modulation (See Mayell: Paragraph 0002, Varying the duty cycle may be referred to as pulse width modulation (PWM) control).
US PGPUB 2019/0114987 to Li discloses that duty cycle modulation is the same as pulse width modulation (See Li: Paragraph 0008, It is well known that a preferred means for controlling the apparent intensity of an LED is pulse width modulation, also referred to as duty cycle modulation).
US PGPUB 2001/0034542 to Mann discloses that duty cycle is equal to pulse width divided by the period (See Mann: Paragraph 0045, The ratio of the pulse width (PW) to the time T (the increment between the pulses) defines the duty cycle).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HARRY Z WANG whose telephone number is (571)270-1716. The examiner can normally be reached 9 am - 3 pm (Monday-Friday).
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/H.Z.W./Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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