DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 20 is rejected under 35 U.S.C 101 because the claimed invention is directed to non-statutory subject matter as follows: Claim 20 recites, “*a computer-readable medium...”. Although, the specification in [0190] discloses, “*Computer-readable media may include computer data storage media or communication media including any medium that facilitates transfer of a computer program from one place to another. In this manner, computer-readable media generally may correspond to: (1) tangible computer-readable storage media, which is non-transitory; or (2) a communication medium such as a signal or a carrier wave", the specification does not limit the claimed storage medium to a non-transitory tangible statutory medium storing the program.
The broadest reasonable interpretation of a claim drawn to a computer readable medium or a storage medium, typically covers forms of non-transitory, tangible media and transitory propagating signals per se in view of the ordinary and customary meaning of memory. A transitory, propagating signal is not a process, machine, manufacture, or composition of matter. Those four categories define the explicit scope and reach of subject matter patentable under 35 U.S.C. 101; thus, such a signal cannot be patentable subject matter. Because the full scope of the claim as properly read in light of the disclosure appears to encompass non-statutory subject matter the claim as a whole is non-statutory.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 15, 20; 2, 3, 4, 5, 7, 8, 9, 12, 13, 14, 16, 17, 18 and 20is/are rejected under 35 U.S.C. 103 as being unpatentable over Eichenberger et al. U.S. Patent No. 8,056,065 in view of Sahu U.S. Pub. No. 2024/0330455 and Harboe et al. U.S. Pub. No. 2025/0341970.
Re: claims 1, 15 and 20 (which are rejected under the same rationale), Eichenberger teaches
1. An apparatus for graphics processing, comprising: a memory; and a processor coupled to the memory, wherein, based at least in part on information stored in the memory, the processor is configured to: (“... data processing system 400 employs a hub architecture... Processing unit 506, main memory 408, processing unit 406 and graphics processor 410 are connected to NB/MCH 402.”; Eichenberger, col. 10, lines 1-3, Fig. 4)
Fig. 4 illustrates a data processing system includes main memory 408, processing unit 406 and graphics processor 410 that are coupled.
(“The processes for illustrative embodiments of the present invention may be performed by processing unit 406 using computer usable program code, which may be located in a memory such as, for example, main memory 408, ROM 424...”; Eichenberger, col. 10, lines 50-55)
The embodiments of the invention are performed by the processing unit using computer usable code stored in the memory 408.
obtain a representation of source code; (“For example, in a distributed data processing system, the source code may be provided such as by a client data processing device, to a server or other data processing device that runs a compiler for compiling the source code into executable code.”; Eichenberger, col. 8, lines 58-62)
The source code is provided to a processing device that runs a compiler (obtain a representation of source code).
Eichenberger is silent regarding identify that the representation comprises a first set of decomposable write memory accesses; calculate a second set of slicing criteria based on the identified first set of decomposable write memory accesses, however, Sahu and Harboe teach
identify that the representation comprises a first set of decomposable write memory accesses; (“... the term “vulnerability detection machine learning model framework” may refer to a data construct that describes parameters, hyperparameters, and/or defined operations of a machine learning model that is configured to match source code from each of one or more source code files to one or more program slices by parsing the source code and mapping one or more portions of the source code to the one or more program slices, and generate a vulnerability prediction for each of one or more source code files.”; Sahu,[0054])
The source code (identify that the source code) is parsed (decomposable) and mapped to one or more program slices.
calculate a second set of slicing criteria based on the identified first set of decomposable write memory accesses; (“... a training dataset may be generated by: (i) receiving one or more training source code files and one or more vulnerability classes associated with the one or more training source code files, (ii) receiving one or more syntax features for each of the one or more vulnerability classes, (iii) determining a program slicing criterion based on the one or more syntax features...,”; Sahu, [0058])
The source code is received and used to determine a program slicing criterion. Eichenberger is silent regarding the source code representation including write memory accesses. However, Harboe teaches this limitation.
(“A compiled program is divided into slice tasks. Slice tasks comprise code sequences of various sizes which include at least one load instruction... The first slice task can include one or more instructions such as arithmetic and logical instructions, memory access instructions, and so on... Discussed previously, the first slice can include one or more instructions, where the instructions can include arithmetic, logical, and memory access instructions, and so on. The memory access instructions can include store instructions and load instructions.”; Harboe, [0035], [0037], [0039])
The program (source code representation) is divided into slice tasks (decomposable). The first slice task includes memory access instructions such as store instructions (decomposable write memory access instructions). Harboe is combined with Eichenberger and Sahu such that the source code representation of Eichenberger includes the store instructions (decomposable write memory accesses) of Harboe. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the system of Eichenberger by adding the feature of decomposable write memory accesses, in order to detect multiclass vulnerabilities and locate precise locations of vulnerabilities in source code in precision, as taught by Sahu ([0029]), and in order to increase performance by executing multiple slices on two or more compute slices thereby enabling parallelized operations, as taught by Harboe ([0036]).
Eichenberger and Harboe are silent regarding generate a plurality of representation slices based on the representation of the source code and the calculated second set of slicing criteria; and output an indicator of the generated plurality of representation slices, however Sahu teaches
generate a plurality of representation slices based on the representation of the source code and the calculated second set of slicing criteria; (“... (iv) extracting one or more program slices from the one or more training source code files based on the program slicing criterion...”; Sahu, [0058])
One or more program slices are extracted (generate a plurality of representation slices) from the source code and based on the program slicing criterion (based on the representation of the source code and the calculated set of slicing criteria).
and output an indicator of the generated plurality of representation slices. (“... and (v) labeling the one or more program slices with the one or more vulnerability classes.”; Sahu, [0058])
The one or more program slices are labeled with vulnerability classes (output an indicator of the generated plurality of representation slices). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the system of Eichenberger by adding the feature of generate a plurality of representation slices based on the representation of the source code and the calculated second set of slicing criteria; and output an indicator of the generated plurality of representation slices, in order to detect multiclass vulnerabilities and locate precise locations of vulnerabilities in source code in precision, as taught by Sahu ([0029]).
Claim 20 is a medium analogous to the apparatus of claim 1, is similar in scope and is rejected under the same rationale. Claim 20 has an additional limitation. Re: claim 20, Eichenberger teaches
20. A computer-readable medium storing computer executable code, the code when executed by a processor, causes the processor to: (“The processes for illustrative embodiments of the present invention may be performed by processing unit 406 using computer usable program code, which may be located in a memory such as, for example, main memory 408, ROM 424...”; Eichenberger, col. 10, lines 50-55)
The embodiments of the invention are performed by the processing unit using computer usable code stored in the memory 408.
Re: claim 2, Eichenberger, Sahu and Harboe teach
2. The apparatus of claim 1, wherein the representation comprises at least one of the source code or a transformed form of the source code. (“For example, in a distributed data processing system, the source code may be provided such as by a client data processing device, to a server or other data processing device that runs a compiler for compiling the source code into executable code.”; Eichenberger, col. 8, lines 58-62)
The source code (the representation comprises at least one of the source code) is provided to a processing device that runs a compiler for compiling the source code into executable code (or a transformed form of the source code).
Re: claim 3, Eichenberger, Sahu and Harboe teach
3. The apparatus of claim 1, wherein the first set of decomposable write memory accesses comprises at least one of: a third set of uniform data accesses; a fourth set of divergent data accesses; or a fifth set of memory oversubscription buffer accesses that exceed a threshold value. (“A slice task executing non-speculatively can include the head task slice and therefore can have priority over access by speculatively executing slice tasks... The compute slices can include the head slice, a tail slice, intermediate slices, and so on. Recall that compute slice can be executing a slice task non-speculatively (e.g., the head slice) or speculatively (e.g., other slices)... since the successor compute slices were executing speculatively, a row associated only with the successor slices can be evicted so that the head slice can continue executing. In the case where loads and/or stores from the head slice fill the GMOT, back pressure can be applied to the head slice until the GMOT is able to clear entries, making space for additional loads and/or stores.”; Harboe, [0040], [0041])
When the store slice tasks (decomposable write memory accesses) are executed and the stores fill the GMOT (fifth set of memory oversubscription buffer accesses that exceed a threshold value), back pressure is applied to the head slice until the GMOT is able to clear entries, making space for additional stores. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the system of Eichenberger by adding the feature of the first set of decomposable write memory accesses comprises at least one of: a third set of uniform data accesses; a fourth set of divergent data accesses; or a fifth set of memory oversubscription buffer accesses that exceed a threshold value, in order to increase performance by executing multiple slices on two or more compute slices thereby enabling parallelized operations, as taught by Harboe ([0036]).
Re: claims 4 and 16 (which are rejected under the same rationale), Eichenberger, Sahu and Harboe teach
4. The apparatus of claim 1, wherein, to identify that the representation comprises the indicator of the first set of decomposable write memory accesses, the processor is configured to: identify that each of the first set of decomposable write memory accesses satisfies a third set of type criteria; identify that each of the first set of decomposable write memory accesses satisfies a fourth set of control flow (CF) criteria; identify that each of the first set of decomposable write memory accesses satisfies a fifth set of data dependency criteria; or identify whether an index set of the first set of decomposable write memory accesses is associated with a sixth set of predicates. (“... and (v) labeling the one or more program slices with the one or more vulnerability classes.”; Sahu, [0058])
The source code include program slices that are labeled with at least one vulnerability class (identify that each of the first set of decomposable write memory accesses satisfies a third type of criterial).
(“... a PDB comprises a data construct that describes a representation of data and control-flow dependencies between program statements... an operational example of a PDG is depicted in Fig. 9. As depicted in Fig. 9, PDG 900 comprises nodes associated with each program statement of source code 902, a first set of edges representative of data dependencies between program statements, and a second set of edges representative of control dependencies between program statements.”; Sahu, [0088], Fig. 9)
The PDB describes a representation of data and control-flow dependencies (satisfies a fourth set of control flow (CF) criteria) between program statements. Fig. 9 illustrates nodes associated with each program statement, where the edges represent data dependencies (satisfies a fifth set of data dependency criteria) between program statements and the edges represent control dependencies (satisfies a fourth set of control flow (CF) criteria) between program statements. Sahu is combined with Eichenberger and Harboe such that the program slices of Sahu include the include the store instructions (decomposable write memory accesses) of Harboe. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the system of Eichenberger by adding the feature of to identify that the representation comprises the indicator of the first set of decomposable write memory accesses, the processor is configured to: identify that each of the first set of decomposable write memory accesses satisfies a third set of type criteria; identify that each of the first set of decomposable write memory accesses satisfies a fourth set of control flow (CF) criteria; identify that each of the first set of decomposable write memory accesses satisfies a fifth set of data dependency criteria; or identify whether an index set of the first set of decomposable write memory accesses is associated with a sixth set of predicates, in order to detect multiclass vulnerabilities and locate precise locations of vulnerabilities in source code in precision, as taught by Sahu ([0029]).
Re: claim 5, Eichenberger, Sahu and Harboe teach
5. The apparatus of claim 4, wherein the third set of type criteria comprise at least one of: a statically known data type; a statically bound pair of source operands and transitive dependencies; an aggregate type; a seventh set of sources comprising the aggregate type; an iterated access; an underlying object that exhausts an available hardware limit; a target that does not escape a corresponding shader stage until completion of the corresponding shader stage; or an eighth set of operands that consist of read-only variables or program state variables (PSVs) that do not escape the corresponding shader stage until the completion of the corresponding shader stage. (“... and (v) labeling the one or more program slices with the one or more vulnerability classes... the term “vulnerability class” may refer to a data construct that describes a label associated with a type of vulnerability.”; Sahu, [0058], [0063])
The program slices are labeled with a corresponding vulnerability class (the third type of criteria comprises at least one of a statically known data type). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the system of Eichenberger by adding the feature of the third set of type criteria comprise at least one of: a statically known data type; a statically bound pair of source operands and transitive dependencies; an aggregate type; a seventh set of sources comprising the aggregate type; an iterated access; an underlying object that exhausts an available hardware limit; a target that does not escape a corresponding shader stage until completion of the corresponding shader stage; or an eighth set of operands that consist of read-only variables or program state variables (PSVs) that do not escape the corresponding shader stage until the completion of the corresponding shader stage, in order to detect multiclass vulnerabilities and locate precise locations of vulnerabilities in source code in precision, as taught by Sahu ([0029])
Re: claim 7, Eichenberger, Sahu and Harboe teach
7. The apparatus of claim 4, wherein the fifth set of data dependency criteria comprise at least one of: a target that is not subsequently read by a first memory access in a corresponding shader stage; a seventh set of sources corresponding with a memory access of the first set of decomposable write memory accesses that are not used by a second memory access; an eighth set of sources that are not used by the second memory access, wherein the seventh set of sources are transitively dependent on the eighth set of sources; a ninth set of reads that are not self-referential; or a tenth set of writes that are not self-referential. (“As depicted in Fig. 9, PDG 900 comprises nodes associated with each program statement of source code 902, a first set of edges representative of data dependencies between the program statements, and a second set of edges representative of control dependencies between he program statements.”; Sahu, [0088], Fig. 9)
Fig. 9 illustrates a program dependency graph that the transitive dependency of sources. For example, elements 4, 1 and 6 are considered to be the eighth set of sources that are not used by the second memory access (elements 5, 3 and 7 are considered to perform the second memory access (5 accesses the memory at 2)). For example, 6 is considered to be transitively dependent upon 5 (the seventh set of sources are transitively dependent on the eighth set of sources). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the system of Eichenberger by adding the feature of the fifth set of data dependency criteria comprise at least one of: a target that is not subsequently read by a first memory access in a corresponding shader stage; a seventh set of sources corresponding with a memory access of the first set of decomposable write memory accesses that are not used by a second memory access; an eighth set of sources that are not used by the second memory access, wherein the seventh set of sources are transitively dependent on the eighth set of sources; a ninth set of reads that are not self-referential; or a tenth set of writes that are not self-referential, in order to detect multiclass vulnerabilities and locate precise locations of vulnerabilities in source code in precision, as taught by Sahu ([0029])
Re: claims 8 and 17 (which are rejected under the same rationale), Eichenberger, Sahu and Harboe teach
8. The apparatus of claim 4, wherein, to calculate the second set of slicing criteria, the processor is configured to: split an index set of a decomposable write memory access of the first set of decomposable write memory accesses based on the sixth set of predicates in response to an identification that the index set is associated with the sixth set of predicates. (“A program slice may comprise an extraction of one or more program statements from source code based on a program slice criterion.”; Sahu, [0074])
A program slice comprises an extraction program statements from source code (split an index of a set of decomposable write memory access of the first set of decomposable write memory accesses) based on a program slice criterion (based on a sixth set of predicates).
(“Determining the program slicing criterion may comprise determining one or more potential vulnerability candidates by performing static analysis on the one or more training source code files and matching the program statements of the source code files with the one or more syntax features. As such ,program statements that match the one or more syntax features may be determined as potential vulnerability candidates. Potential vulnerability candidates may then be identified as program slicing criterion. It is noted that the potential vulnerability candidates may be either non-vulnerable or vulnerable.”; Sahu, [0084])
The program slicing criterion comprises determining potential vulnerability candidates in the source code. Program statements that match the syntax features are determined to be potential vulnerability candidates, which are then identified as program slicing criterion. The potential vulnerability candidates are either non-vulnerable or vulnerable (associated with the sixth set of predicates).
(“For example, extracting one or more program slices may comprise generating a source code subset based on a program slicing criterion associated with potential vulnerability candidates identified from the one or more training source code files.”; Sahu, [0089])
Extracting program slices (split an index) includes generating a source code subset based on program slicing criterion (based on the sixth set of predicates) associated with potential vulnerability candidates (in response to an identification that the index is associated with the sixth set of predicates). Sahu is combined with Eichenberger and Harboe such that the program slices of Sahu include the include the store instructions (decomposable write memory accesses) of Harboe. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the system of Eichenberger by adding the feature of to calculate the second set of slicing criteria, the processor is configured to: split an index set of a decomposable write memory access of the first set of decomposable write memory accesses based on the sixth set of predicates in response to an identification that the index set is associated with the sixth set of predicates, in order to detect multiclass vulnerabilities and locate precise locations of vulnerabilities in source code in precision, as taught by Sahu ([0029]).
Re: claims 9 and 18 (which are rejected under the same rationale), Eichenberger, Sahu and Harboe teach
9. The apparatus of claim 4, wherein, to calculate the second set of slicing criteria, the processor is configured to: split an index set of a decomposable write memory access of the first set of decomposable write memory accesses in response to an identification that the index set is not associated with any predicates. (“A program slice may comprise an extraction of one or more program statements from source code based on a program slice criterion.”; Sahu, [0074])
A program slice comprises an extraction program statements from source code (split an index of a set of decomposable write memory access of the first set of decomposable write memory accesses) based on a program slice criterion.
(“Determining the program slicing criterion may comprise determining one or more potential vulnerability candidates by performing static analysis on the one or more training source code files and matching the program statements of the source code files with the one or more syntax features. As such ,program statements that match the one or more syntax features may be determined as potential vulnerability candidates. Potential vulnerability candidates may then be identified as program slicing criterion. It is noted that the potential vulnerability candidates may be either non-vulnerable or vulnerable.”; Sahu, [0084])
The program slicing criterion comprises determining potential vulnerability candidates in the source code. Program statements that match the syntax features are determined to be potential vulnerability candidates, which are then identified as program slicing criterion. The potential vulnerability candidates are either non-vulnerable (not associated with the sixth set of predicates) on vulnerable.
(“For example, extracting one or more program slices may comprise generating a source code subset based on a program slicing criterion associated with potential vulnerability candidates identified from the one or more training source code files.”; Sahu, [0089])
Extracting program slices (split an index) includes generating a source code subset based on program slicing criterion (based on the sixth set of predicates) associated with potential vulnerability candidates (in response to an identification that the index is associated with the sixth set of predicates).
(“... certain program slices may represent source code that is semantically relevant to one or more vulnerabilities and other program slices may represent source code that is not semantically relevant to vulnerabilities.”; Sahu, [0090])
Certain extracted program slices represent source code that is semantically relevant to vulnerabilities (is associated with predicates) and other program slices represent source code that is not semantically relevant to vulnerabilities (in response to an identification that the index is not associated with an predicates). Sahu is combined with Eichenberger and Harboe such that the program slices of Sahu include the include the store instructions (decomposable write memory accesses) of Harboe. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the system of Eichenberger by adding the feature of to calculate the second set of slicing criteria, the processor is configured to: split an index set of a decomposable write memory access of the first set of decomposable write memory accesses in response to an identification that the index set is not associated with any predicates, in order to detect multiclass vulnerabilities and locate precise locations of vulnerabilities in source code in precision, as taught by Sahu ([0029]).
Re: claim 12. Eichenberger, Sabu and Harboe teach
12. The apparatus of claim 1, wherein, to output the indicator of the generated plurality of representation slices, the processor is configured to: schedule each program slice of the generated plurality of representation slices for asynchronous launch relative to other representation slices of the generated plurality of representation slices. (“Control is provided to the hardware by the control unit which allocates slice tasks to compute slices. Once issued, the slice tasks can execute independently from the control unit and other compute slices until they are either halted by the control unit, indicate an exception, finish executing, etc... Because the processing unit includes multiple compute slices, slice tasks can be executed in parallel”; Harboe, [0028], [0037])
Slice tasks (program slices) are executed independently and in parallel (schedule each program slice of the generated plurality of representation slices for asynchronous launch relative to other representative slices of the generated plurality of representation slices). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the system of Eichenberger by adding the feature of to output the indicator of the generated plurality of representation slices, the processor is configured to: schedule each program slice of the generated plurality of representation slices for asynchronous launch relative to other representation slices of the generated plurality of representation slices, in order to increase performance by executing multiple slices on two or more compute slices thereby enabling parallelized operations, as taught by Harboe ([0036]).
Re: claim 13, Eichenberger, Sabu and Harboe
13. The apparatus of claim 12, wherein, to output the indicator of the generated plurality of representation slices, the processor is further configured to: calculate a cost for an execution of the generated plurality of representation slices, wherein, to schedule each program slice of the generated plurality of representation slices, the processor is configured to schedule each program slice of the generated plurality of representation slices in response to the calculated cost being greater than or equal to a threshold value. (“... since the successor compute slices were executing speculatively, a row associated only with the successor slices can be evicted so that the head slice can continue executing. In the case where loads and/or stores from the head slice fill the GMOT, back pressure can be applied to the head slice until the GMOT is able to clear entries, making space for additional loads and/or stores.”; Harboe, [0041])
The cost is considered to be the amount of storage in the GMOT for the store slice tasks (calculate a cost for an execution of the generated plurality of representation slices). The cost is considered to be above a threshold when the when the stores fill the GMOT. When the store slice tasks are executed and the stores fill the GMOT, back pressure is applied to the head slice until the GMOT is able to clear entries, making space for additional stores (schedule each program slice of the generated plurality of representation slices in response to the calculated cost being greater than or equal to a threshold value). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the system of Eichenberger by adding the feature of , to output the indicator of the generated plurality of representation slices, the processor is further configured to: calculate a cost for an execution of the generated plurality of representation slices, wherein, to schedule each program slice of the generated plurality of representation slices, the processor is configured to schedule each program slice of the generated plurality of representation slices in response to the calculated cost being greater than or equal to a threshold value, in order to increase performance by executing multiple slices on two or more compute slices thereby enabling parallelized operations, as taught by Harboe ([0036]).
Re: claim 14, Eichenberger, Sabu and Harboe
14. The apparatus of claim 1, wherein, to output the indicator of the generated plurality of representation slices, the processor is further configured to: calculate a cost for an execution of the generated plurality of representation slices; and output a second indicator of the calculated cost for the execution of the generated plurality of representation slices. (“... since the successor compute slices were executing speculatively, a row associated only with the successor slices can be evicted so that the head slice can continue executing. In the case where loads and/or stores from the head slice fill the GMOT, back pressure can be applied to the head slice until the GMOT is able to clear entries, making space for additional loads and/or stores.”; Harboe, [0041])
The cost is considered to be the amount of storage in the GMOT for the store slice tasks (calculate a cost for an execution of the generated plurality of representation slices). When the store slice tasks are executed and the stores fill the GMOT, back pressure is applied to the head slice until the GMOT is able to clear entries (second indicator), making space for additional stores (output a second indicator of the calculated cost for the execution of the generated plurality of representation slices). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the system of Eichenberger by adding the feature of to output the indicator of the generated plurality of representation slices, the processor is further configured to: calculate a cost for an execution of the generated plurality of representation slices; and output a second indicator of the calculated cost for the execution of the generated plurality of representation slices, in order to increase performance by executing multiple slices on two or more compute slices thereby enabling parallelized operations, as taught by Harboe ([0036]).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eichenberger, Sahu and Harboe as applied to claim 4 above, and further in view of Allen U.S. Patent No. 9,239,716.
Re: claim 6, Eichenberger, Sahu and Harboe are silent regarding the fourth set of CF criteria comprise at least one of: a seventh set of sources corresponding with a memory access of the first set of decomposable write memory accesses that are computed or are defined outside of irreducible regions, however, Allen teaches
6. The apparatus of claim 4, wherein the fourth set of CF criteria comprise at least one of: a seventh set of sources corresponding with a memory access of the first set of decomposable write memory accesses that are computed or are defined outside of irreducible regions; or an eighth set of sources that are computed or are defined outside of the irreducible regions, wherein the seventh set of sources are transitively dependent on the eighth set of sources.
(“... a program definition of the application may be divided into program definition slices. The program definition slices may include a baseline slice and one or more supplemental slices. In some cases, the baseline slice includes mandatory program components, and a supplemental slice includes optional program components.”; Allen, col. 1, lines 49-54)
The program definition slices include a baseline slice and at least on supplemental slice. The baseline slice includes mandatory program components, which are considered to be irreducible regions. And, the supplemental slice includes optional components that are considered to be defined outside of irreducible regions. Martin is combined with Eichenberger, Sahu and Harboe such that the program definition slices of Martin include the include the store instructions (decomposable write memory accesses) of Harboe. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the system of Eichenberger by adding the feature of the fourth set of CF criteria comprise at least one of: a seventh set of sources corresponding with a memory access of the first set of decomposable write memory accesses that are computed or are defined outside of irreducible regions, in order to allow efficient delivery of the application such that the slices may be patched together to recreate a portion of the program definition, as taught by Allen (col. 1, lines 56-60).
Claim(s) 10, 11 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Eichenberger, Sahu and Harboe as applied to claims 1, 9 and 18 above, and further in view of Martin et al. U.S. Pub. No. 2011/0252411.
Re: claims 10 and 19 (which are rejected under the same rationale), Eichenberger, Sahu and Harboe are silent regarding to split the index set of the decomposable write memory access, the processor is configured to: split the index set of the decomposable write memory access based on a resource size threshold, however, Martin teaches
10. The apparatus of claim 9, wherein, to split the index set of the decomposable write memory access, the processor is configured to: split the index set of the decomposable write memory access based on a resource size threshold. (“For example, as shown in Fig. 6, static analyzer 600 may utilize the static analysis to break TCE code 530 into portion(s) of TCE code, as indicated by numeral 620. Static analyzer 600 may provide portion(s) 620 of TCE code 530 to dynamic threshold component 610.”; Martin, [0057], Fig. 6)
Fig. 6 illustrates that the TCE code is broken into portions 620 (split the index set of decomposable write memory access) and provided to the dynamic threshold component 610.
(“... dynamic threshold component 610 may compare a size ... of each portion 620 of TCE code 530 to the size threshold, and may compare a degree of parallelism of each portion 620 of TCE code 530 to the degree of parallelism threshold. Dynamic threshold component 610 may determine which portions 620 of TCE code 530 are more efficiently executed by GPU 130, or more efficiently executed by CPU 140, based on the comparisons of the size threshold and/or the degree of parallelism threshold.”; Martin, [0059])
The dynamic threshold component compares a size of each portion to the TCE code to the size threshold (resource size threshold) and determines which portions of TCE code are more efficiently executed by the GPU and which portions are more efficiently executed by the CPU (split the index set of the decomposable write memory access based on a resource size threshold). Martin is combined with Eichenberger, Sahu and Harboe, such that the TCE code of Martin includes the decomposable write memory access of Sahu. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the system of Eichenberger by adding the feature of to split the index set of the decomposable write memory access, the processor is configured to: split the index set of the decomposable write memory access based on a resource size threshold in order to enable the GPU compiler to provide a quicker and easier way for users to produce GPU-executable code, as taught by Martin ([0051]).
Re: claim 11, Eichenberger, Sahu and Harboe are silent regarding to output the indicator of the generated plurality of representation slices, the processor is configured to: output the indicator of the generated plurality of representation slices to a compiler, however, Martin teaches
11. The apparatus of claim 1, wherein, to output the indicator of the generated plurality of representation slices, the processor is configured to: output the indicator of the generated plurality of representation slices to a compiler. (“As further shown in Fig. 5, code type determiner 500 may provide, to GPU compiler 510, the portion(s) of TCE code 530 determined to be more efficiently executed by GPU 130... and may provide, to CPU compiler 520, the portion(s) of TCE code 530 determined to be more efficiently executed by CPU 140...”; Martin, [0049], Fig. 5)
The code type determiner determines (indicates) that certain TCE code portions (representation slices) will be more efficiently processed by the GPU. The code type determiner then provides these TCE portions (representation slices) to the GPU compiler (output indicator of the generated plurality of representation slices to a compiler). Therefore, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date, to modify the system of Eichenberger by adding the feature of to output the indicator of the generated plurality of representation slices, the processor is configured to: output the indicator of the generated plurality of representation slices to a compiler, in order to enable the GPU compiler to provide a quicker and easier way for users to produce GPU-executable code, as taught by Martin ([0051]).
Conclusion
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/Donna J. Ricks/Examiner, Art Unit 2618
/DEVONA E FAULK/Supervisory Patent Examiner, Art Unit 2618