DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The instant application having Application No. 18/670,512 has a total of 22 claims pending in the application; there are 4 independent claims and 18 dependent claims, all of which are ready for examination by the examiner.
INFORMATION CONCERNING OATH/DECLARATION
Oath/Declaration
The applicant’s oath/declaration has been reviewed by the examiner and is found to conform to the requirements prescribed in 37 C.F.R. 1.63.
ACKNOWLEDGEMENT OF REFERENCES CITED BY APPLICANT
As required by M.P.E.P. 609(C), the applicant’s submissions of the Information Disclosure Statement 05/21/2024 is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
REJECTIONS NOT BASED ON PRIOR ART
Claim Rejections - 35 USC § 112(f)
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims 1, 11, 20 and 22 in this application are given their broadest reasonable
interpretation using the plain meaning of the claim language in light of the specification
as it would be understood by one of ordinary skill in the art. The broadest reasonable
interpretation of a claim element (also commonly referred to as a claim limitation) is
limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35
U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35
U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute
for “means” that is a generic placeholder (also called a nonce term or a nonstructural
term having no specific structural meaning) for performing the claimed
function;
(B) the term “means” or “step” or the generic placeholder is modified by functional
language, typically, but not always linked by the transition word “for” (e.g.,
“means for”) or another linking word or phrase, such as “configured to” or “so
that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient
structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a
rebuttable presumption that the claim limitation is to be treated in accordance with 35
U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim
limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth
paragraph, is rebutted when the claim limitation recites sufficient structure, material, or
acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable
presumption that the claim limitation is not to be treated in accordance with 35 U.S.C.
112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim
limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth
paragraph, is rebutted when the claim limitation recites function without reciting
sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are
being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph,
except as otherwise indicated in an Office action. Conversely, claim limitations in this
application that do not use the word “means” (or “step”) are not being interpreted under
35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise
indicated in an Office action.
REJECTIONS BASED ON PRIOR ART
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed, approved immediately upon submission, and reduces waiting time for Terminal Disclaimer to be manually approved. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-4, 7-8, 10-14 and 16-26 are rejected on the ground of nonstatutory double patenting over the claims of 1-22 of U.S. Pat. No. 12,001,693, since the claims, if allowed, would improperly extend the “right to exclude” already granted in patents. Although the conflicting claims are not identical, they are not patentably distinct from each other because the subject matter claimed in the instant application is at least fully disclosed in the reference patents and application.
Claim Rejections - 35 USC § 103
1. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1-4, 7-8, 10-14 and 16-26 are rejected under 35 U.S.C. 103(a) as being unpatentable over Fitzpatrick et al. (US pub. 2022/0044756), hereinafter, “Fitzpatrick”, in view of Berman et al. (US pat. 11,221,769), hereinafter, “Berman”.
3. As per claims 1, 11, 20, 21 and 22, Fitzpatrick discloses a device (integrated circuit memory device 130 of fig. 2) formed on a die, comprising: a non-volatile memory (NVM) array formed on the die (see abstract, which discloses “a group of memory cells formed on an integrated circuit die in the memory device, the memory device may measure signal and noise characteristics of the group of memory cells during execution of the read commands. Based on the signal and noise characteristics the memory sub-system can generate or update, measured during the execution of the read commands a model of changes relevant to reading data from the group of memory cells”); and processing circuitry (see fig. 2) formed on the die and configured to: read data from the NVM array using a first read voltage level set to add (to ‘add’ is being interpreted as to establish/have) noise into the data to obtain a noisy version of the data (see paragraph 0023); obtain corresponding data without added noise (see paragraph 0032); receive a value specifying an amount of noise to be added into additional data read from the NVM array (see paragraph 0061 and fig. 3); adjust the first read voltage level to a second read voltage level based on the received value (see paragraph 0061 and fig. 3); and read the additional data from the NVM array using the second read voltage level to add the specified amount of noise into the additional data read from the NVM array (see paragraph 0061 and fig. 3).
but fails to expressly discloses compare the corresponding data with the noisy version of the data to determine an amount of noise added to the data by using the first read voltage level.
Berman discloses compare the corresponding data with the noisy version of the data to determine an amount of noise added to the data by using the first read voltage level [see col. 13, line 46 to col. 14, line 2, particularly “for example, if the difference of means between the clean level data and the noised level data is 150 mV, and is corrected to −10, performance and efficiency of the neural network will increase, since the neural network will only have to correct about (10+noise_std) mV instead of (150+noise_std) mV per memory cell”].
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Berman’s teaching of a method of performing noise cancellation on a memory device using a neural network, into Fitzpatrick’s teaching of a memory sub-system configured to generate or update a model for reading memory cells in a memory device, for the ability/benefit of configuring several bits of data to be stored in a plurality memory cells.
4. As per claims 2 and 12, the combination of Fitzpatrick and Berman discloses “The device of claim 1” [See rejection to claim 1 above], wherein the processing circuitry is further configured to compare the corresponding data with the noisy version of the data by XORing the corresponding data with the noisy version of the data to obtain a count of bit differences (see col. 11, line 45 to col. 12, line 29 of Berman and paragraph 0038 of Fitzpatrick, which discloses “The result of the XOR operation can be used as soft bit data for decoding the hard bit data read using the optimized/calibrated read voltage. In some implementations, a larger offset can be used to read another set of soft bit data indicating whether the memory cells provide the same reading at the locations according to the larger offset around the optimized/calibrated read voltage”).
5. As per claims 3 and 13, the combination of Fitzpatrick and Berman discloses “The device of claim 1” [See rejection to claim 1 above], wherein the processing circuitry is further configured to obtain the corresponding data by being further configured to: set the read voltage level to a third read voltage level selected to avoid adding noise; and re-read the same data from the NVM array to obtain an alternate version of the data that has no added noise (see fig. 7 and col. 11, line 45 to col. 12, line 29 of Berman and paragraph 0038 of Fitzpatrick).
6. As per claims 4 and 14, the combination of Fitzpatrick and Berman discloses “The device of claim 3” [See rejection to claim 3 above], wherein the processing circuitry is further configured to: obtain a correct version of the data; compare the correct version of the data to the alternate version of the data to obtain a second value that is representative of an amount of preexisting noise in the data; and further adjust the third read voltage level based on the second value (see fig. 7 and col. 11, line 45 to col. 12, line 29 of Berman and paragraph 0038 of Fitzpatrick).
7. As per claim 7, the combination of Fitzpatrick and Berman discloses “The device of claim 1” [See rejection to claim 1 above], wherein the data is neural network data, and wherein the processing circuitry is further configured to use the additional data in a neural network (see abstract of Berman).
8. As per claim 8, the combination of Fitzpatrick and Berman discloses “The device of claim 7” [See rejection to claim 7 above], wherein the processing circuitry is further configured to use the additional data in the neural network as an augmented training data set to train or test the neural network to recognize images (see fig. 7 of Berman and paragraph 0061 of Fitzpatrick).
9. As per claim 10, the combination of Fitzpatrick and Berman discloses “The device of claim 1” [See rejection to claim 1 above], wherein the NVM array comprises at least one of a NAND array, a NOR array, phase-change memory (PCM) array, magneto-resistive random access memory (MRAM) arrays, a resistive random access memory (ReRAM) array, or a 3D XPoint (3DXP) array (see paragraph 0053 of Fitzpatrick).
10. As per claim 16, the combination of Fitzpatrick and Berman discloses “The method of claim 13” [See rejection to claim 13 above], further comprising: obtaining an indication of an amount of preexisting noise in the data; and adjusting the third read voltage level based on the amount of preexisting noise (see col. 16, lines 23-49 of Berman and paragraph 0061 of Fitzpatrick).
11. As per claim 17, the combination of Fitzpatrick and Berman discloses “The method of claim 16” [See rejection to claim 16 above], wherein the indication of the amount of preexisting noise in the data is based on a count of errors corrected via error correction coding (ECC) in the data that is re-read (see paragraph 0074 of Fitzpatrick).
12. As per claim 18, the combination of Fitzpatrick and Berman discloses “The method of claim 16” [See rejection to claim 16 above], wherein the indication of the amount of preexisting noise in the data is based on a count of digital-to-analog (DAC) operations performed during low-density parity-check code (LDPC) decoding of the data that is re-read (see paragraph 0074 of Fitzpatrick).
13. As per claim 19, the combination of Fitzpatrick and Berman discloses “The method of claim 16” [See rejection to claim 16 above], wherein the indication of the amount of preexisting noise in the data is based on an amount of change in a voltage threshold (VT) between an initial write verification read voltage level and a current read voltage level (see fig. 3 of Fitzpatrick).
14. As per claims 23 and 25, the combination of Fitzpatrick and Berman discloses “The device of claim 1” [See rejection to claim 1 above], wherein the processing circuitry is configured to read the data from the NVM array using the first read voltage level by being further configured to: determine a noise-minimizing read voltage level that minimizes an amount of noise occurring within data read from the NVM array; and set the first read voltage level to a level different from the noise-minimizing read voltage level to add the noise into the data read from the NVM array, wherein the added noise is greater than an amount of noise occurring using the noise-minimizing read voltage level (see fig. 7 and col. 11, line 45 to col. 12, line 29 of Berman and paragraph 0038 of Fitzpatrick).
15. As per claims 24 and 26, the combination of Fitzpatrick and Berman discloses “The device of claim 1” [See rejection to claim 1 above], wherein the processing circuitry is further configured to receive the value specifying the amount of noise by being further configured to: receive a value specifying a percentage of data degradation (see fig. 7 and col. 11, line 45 to col. 12, line 29 of Berman and paragraphs 0038 and 0061 of Fitzpatrick).
CLOSING COMMENTS
CONCLUSION
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the
application as recommended by M.P.E.P. 707.07(i):
a (1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-4, 7-8, 10-14 and 16-26 have received a first action on the merits and are subject of a first action non-final.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the
Examiner should be directed to Ernest Unelus whose telephone number is (571) 272-
8596. The examiner can normally be reached on Monday to Friday 9:00 AM to 5:00PM.
IMPORTANT NOTE
If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner's supervisor, Mr. Idriss Alrobaye, can be reached at the following telephone number: Area Code (571) 270-1023.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through private PAIR only. For more information about the PMR system, see her//pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217- 91 97 (toll-free).
/Ernest Unelus/
Primary Examiner
Art Unit 2181
Prosecution Insights