Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 8-10, and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by An et al. (US 2021/0028286).
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Regarding claim 1, An discloses a semiconductor device [Fig. 25], comprising:
a substrate (100) comprising a first active region (N) and a second active region (P) [Fig. 25];
a first gate conductive pattern (225a) that extends conformally in a first recess (101b) in the first active region (N) [Fig. 25]; and
a second gate conductive pattern (consider the stack of layers 216a and 225a) that at least partially fills a second recess (101a) in the second active region (P) [Fig. 25],
wherein the first gate conductive pattern (225a) has a first thickness (consider the thickness of the stack comprising layers 222a and 224a) in a horizontal direction on an inner lateral surface of the first recess (101b) [Fig. 25],
wherein the second gate conductive pattern (216a/225a) has a second thickness (consider the thickness of the stack comprising layers 216a and 225a) in the horizontal direction on an inner lateral surface of the second recess [Fig. 25], and
wherein the first thickness (thickness comprising layers 222a and 224a) is less than the second thickness (thickness comprising layers 216a, 222a and 224a) [Fig. 25].
Regarding claim 2, An discloses wherein a first work function (consider 222a comprising La) of the first gate conductive pattern (225a) is less than a second work function of the second gate conductive pattern (216a and/or 224a comprising TiN) [Fig. 25, and paragraphs 0038-0041, 0149, 0151 and 0169].
Regarding claim 8, An discloses a first gate dielectric pattern (214a) between the first recess (101b) and the first gate conductive pattern (225a) [Fig. 25]; and
a second gate dielectric pattern (214a) between the second recess (101a) and the second gate conductive pattern (216a/225a) [Fig. 25],
wherein the first and second gate dielectric patterns (214a, which is similar to layer 104a) include a high-k material [paragraph 0035].
Regarding claim 9, An discloses wherein the first and second gate dielectric patterns are free of one or more of lanthanum (La) and aluminum (Al) [paragraph 0035].
Regarding claim 10, An discloses a lower gate electrode (228a) on the first gate conductive pattern, wherein the lower gate electrode at least partially fills the first recess (101b) [Fig. 25]. In addition, An discloses an additional embodiment in which a lower gate electrode layer (226a) is provided [Figs. 19 and 25, and paragraphs 0160, 0162, 0179, 0186 and 0190].
Regarding claim 13, An discloses a semiconductor device, comprising:
a substrate (100) comprising a first active region (N) and a second active region (P) [Fig. 25];
a first gate conductive pattern (consider the embodiment in which layer 216a is not removed from Figure 25, resulting in a stacked structure comprising layers 216a and 225a) that extends conformally in a first recess (101b) of the first active region (N) [Figs. 19 and 25, paragraphs 0160, 0162, 0179, 0186, and 0190]; and
a second gate conductive pattern (216a/225a) that at least partially fills a second recess (101a) of the second active region [Fig. 25],
wherein the first gate conductive pattern (216a/225a) comprises a first p-type conductive pattern (216a: TiN) and a first n-type conductive pattern (222a: La) that are sequentially stacked and extend conformally in the first recess (101b) [Figs. 19 and 25, paragraphs 0038-0041, 0149, 0151, 0169, 0186 and 0190],
wherein the second gate conductive pattern (216a/225a) comprises a second p-type conductive pattern (216a) that extends conformally in the second recess (101a) of the second active region (P) and a second n-type conductive pattern (222a) that is on the second p-type conductive pattern and at least partially fills a portion of the second recess that is unoccupied by the second p-type conductive pattern [Figs. 19 and 25, paragraphs 0038-0041, 0149, 0151, 0169, 0186 and 0190], and
wherein a first work function (consider 222a comprising La) of the first gate conductive pattern (216a/225a) is less than a second work function (216a and/or 224a comprising TiN) of the second gate conductive pattern (216a/225a) [Figs. 19 and 25, and paragraphs 0038-0041, 0149, 0151, 0169, 0186 and 0190].
Regarding claim 16, An discloses a lower gate electrode on the first gate conductive pattern (228a), wherein the lower gate electrode at least partially fills the first recess (101b) [Fig. 25]. In addition, An discloses an additional embodiment in which a lower gate electrode layer (226a) is provided [Figs. 19 and 25, and paragraphs 0160, 0162, 0179, 0186 and 0190].
Regarding claim 18, An discloses a semiconductor device, comprising:
a substrate (100) [Fig. 25] comprising a cell area and a peripheral area [paragraph 0050], the substrate comprising a first active region (N) and a second active region (P) on the peripheral area [Fig. 25 and paragraph 0050];
a first gate conductive pattern (225a) that extends conformally in a first recess (101b) in the first active region (N) [Fig. 25];
a second gate conductive pattern (216a/225a) that at least partially fills a second recess (101a) in the second active region (P) [Fig. 25];
first and second lower gate electrodes (228a and/or 226a) on the first and second gate conductive patterns, respectively [Figs. 19 and 25, and paragraphs 0162, 0179, 0186 and 0190];
first and second upper gate electrodes (232a) on the first and second lower gate electrodes, respectively [Fig. 25];
first and second barrier patterns (230a) between the first and second lower gate electrodes and the first and second upper gate electrodes, respectively [Fig. 25]; and
first and second capping patterns (234) on top surfaces of the first and second upper gate electrodes, respectively [Fig. 25]
wherein the first gate conductive pattern (225a) has a first thickness (consider the thickness of the stack comprising layers 222a and 224a) in a horizontal direction on an inner lateral surface of the first recess (101b) [Fig. 25],
wherein the second gate conductive pattern (216a/225a) has a second thickness (consider the thickness of the stack comprising layers 216a and 225a) in the horizontal direction on an inner lateral surface of the second recess [Fig. 25], and
wherein the first thickness (thickness comprising layers 222a and 224a) is less than the second thickness (thickness comprising layers 216a, 222a and 224a) [Fig. 25].
Regarding claim 19, An discloses wherein a first work function (consider 222a comprising La) of the first gate conductive pattern (225a) is less than a second work function of the second gate conductive pattern (216a and/or 224a comprising TiN) [Fig. 25, and paragraphs 0038-0041, 0149, 0151 and 0169].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over An et al. (US 2021/0028286) in view of Mihara (US 2020/0403073).
Regarding claim 3, An does not disclose wherein each of the first and second gate conductive patterns includes one or more of titanium carbide (TiC) and titanium nitride (TiN) that includes carbon (C).
Mihara teaches wherein each of the first and second gate conductive patterns (MF,MF1,MF3) includes one or more of titanium carbide (TiC) and titanium nitride (TiN) that includes carbon [Figs. 27-28 and paragraphs 0182-0187].
Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to modify An by including one or more of titanium carbide (TiC) and titanium nitride (TiN) that includes carbon (C) as taught by Mihara because it helps to adjust the threshold voltage of the device [paragraph 0186].
Allowable Subject Matter
Claims 13-17 are allowed.
Claims 4-7, 11-12, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSE R DIAZ whose telephone number is (571)272-1727. The examiner can normally be reached Monday-Friday.
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/Jose R Diaz/Primary Examiner, Art Unit 2815
