DETAILED ACTION
This action is responsive to the following: The amendments and arguments made in amendment filed on January 23, 2026.
Claims 1-21 are pending. Claims 1, 9, and 15 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendments filed on January 23, 2026 are entered. Claims 1-21 remain pending. The amendment to the specification overcomes the objection set forth in the FAOM and therefore the rejection is withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
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Claim(s) 1-21 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al (US 10629272) in view of Jia et al (US 20240046980).
Regarding Independent Claim 1, Lu teaches a memory device (Fig. 1A: 100) comprising:
a memory block (Fig. 7A: BLK0) including a plurality of memory cells (Fig. 7A: 701-779);
a peripheral circuit (Fig. 1A: 122, 124, 128) configured to perform a plurality of read voltage applying operations (Fig. 12C-F: WLn, WL_unsel, Vread, VreadK, VrA-G) and a plurality of word line setting operations (Fig. 12C-F: WLn, WL_unsel, 1223, 1224, 1233, 1234, 1243, 1244, 1253) on the memory block (Fig. 7A: BLK0); and
control logic (Fig. 1A: 110) configured to control the peripheral circuit (Fig. 1A: 122, 124, 128) to perform a plurality of word line setting operations (Fig. 12C-F: WLn, WL_unsel, 1223, 1224, 1233, 1234, 1243, 1244, 1253) to set a plurality of word line potentials of word lines included in the memory block (Fig. 7A: BLK0), wherein at least one word line setting operation (Fig. 12C-F: WLn, 1243) among the plurality of word line setting operations is used to set a word line potential higher than a word line potential set by the other word line setting operations.
However, Lu fails to teach wherein during each of the plurality of word line setting operations, a voltage at one level is applied to a selected word line and unselected word lines.
Jia teaches wherein during each of the plurality of word line setting operations (Fig. 6A: 520), a voltage at one level (Fig. 6A: VREAD, T2-T3) is applied to a selected word line (Fig. 6A: 667) and unselected word lines (Fig. 6A: 665).
Jia discloses that applying a single voltage to all of the word lines prior to performing the read operation reduces the rate of temporary read errors that occur when the first read is done on a nonvolatile memory such as NAND flash after being in an idle state. Many readable bits are incorrectly counted as failed bits during this first read and slows down read times by having to reperform the read operations to get accurate failed bit counts. It would therefore improve up read schemes to apply this method to other read operations in flash memories.
It would therefore have been obvious to one of ordinary skill in the are prior to the filing date of the claimed invention to apply the teachings of Jia to the teachings of Lu to produce a method of reading memory cells by applying one voltage level to the selected and unselected word lines prior to performing the read operation on the cells on the selected word line.
Regarding Claim 2, Lu and Jia teach the limitations of Claim 1. Lu further teaches wherein the plurality of memory cells (Fig. 7A: 701-779) are capable of being in an erase state (Fig. 9A: 901) and a plurality of program states (Fig. 9A: 911-917), and the peripheral circuit (Fig. 1A: 122, 124, 128) applies, to a selected word line (Fig. 12C-E: WLn) among the word lines, at least one read voltage (Fig. 12C: VrA) among a plurality of read voltages (Fig. 12C-E: VrA-G) for distinguishing the erase state (Fig. 9A: 901) and the plurality of program states in each of the plurality of read voltage applying operations.
Regarding Claim 3, Lu and Jia teach the limitations of Claim 2. Lu further teaches wherein the peripheral circuit:
performs any one of the plurality of word line setting operations (Fig. 12C-F: WLn, WL_unsel, 1223, 1224, 1233, 1234, 1243, 1244, 1253) between the plurality of read voltage applying operations (Fig. 12C-F: WLn, WL_unsel, VreadK, VrA-G); and
performs the at least one word line setting operation (Fig. 12E: WLn, 1243) just before a specific read voltage applying operation (Fig. 12E: WLn, VrC, VrG) using at least one highest read voltage (Fig. 12E: VrG) among the plurality of read voltage applying operations is performed.
Regarding Claim 4, Lu and Jia teach the limitations of Claim 2. wherein each of the plurality of read voltage applying operations (Fig. 12C-F: WLn, WL_unsel, Vread, VreadK, VrA-G) corresponds to a least significant bit (Fig. 12C: WLn, VrA, VrE), a center significant bit (Fig. 12D: WLn, VrB, VrD, VrF), and a most significant bit of the memory cells (Fig. 12E: WLn, VrC, VrG).
Regarding Claim 5, Lu and Jia teach the limitations of Claim 1. Lu further teaches wherein the peripheral circuit controls (Fig. 1A: 122, 124, 128) the word lines (Fig. 12C-F: WLn, WL_unsel) to have a first voltage level (Fig. 12C: 1223) in the at least one word line setting operation, and controls the word lines to have a second voltage level (Fig. 12D: 1223) in the other word line setting operations, and
wherein the first voltage level (Fig. 12C: 1223) is a positive voltage level higher than zero volts (col 27 lines 42-43 “voltage of plot 1223 is maintained at VrA and then increased from VrA to VrE.”).
Regarding Claim 6, Lu and Jia teach the limitations of Claim 5. Lu further teaches wherein the peripheral circuit (Fig. 1A: 122, 124, 128) controls the word lines to have the second voltage level (Fig. 12D: 1234) before a first read voltage applying operation (Fig. 12D: WLn, VrB, VrD, VrF) among the plurality of read voltage applying operations (Fig. 12C-E: WLn, VrA-G) is performed.
Regarding Claim 7, Lu and Jia teach the limitations of Claim 5. Lu further teaches wherein the peripheral circuit (Fig. 1A: 122, 124, 128) controls the word lines to have the second voltage level (Fig. 12E: Vss) after a last read voltage applying operation among the plurality of read voltage applying operations (Fig. 12C-E: WLn, VrA-G) is performed.
Regarding Claim 8, Lu and Jia teach the limitations of Claim 1. Lu further teaches wherein the control logic (Fig. 1A: 110) includes a word line voltage setting component (Fig. 1A: 116), and wherein the word line voltage setting component (Fig. 1A: 116) is configured to set a word line potential in each of the plurality of word line setting operations (col 7 lines 38-40 “The power control module 116 controls the power and voltages supplied to the word lines, select gate lines, bit lines and source lines during memory operations. It can include drivers for word lines, SGS and SGD transistors and source lines.”).
Regarding Independent Claim 9, Lu teaches a memory device (Fig. 1A: 100) comprising:
a memory block (Fig. 7A: BLK0) including a plurality of memory cells (Fig. 7A: 701-779);
a peripheral circuit (Fig. 1A: 122, 124, 128) configured to alternately perform a plurality of read voltage applying operations (Fig. 12C-F: WLn, WL_unsel, Vread, VreadK, VrA-G) and a plurality of word line setting operations (Fig. 12C-F: WLn, WL_unsel, 1223, 1224, 1233, 1234, 1243, 1244, 1253) on the memory block (Fig. 7A: BLK0); and
control logic (Fig. 1A: 110) configured to set a first specific word line setting operation among the plurality of word line setting operations, which is performed just before a first specific read voltage (Fig. 12E: WLn, VrG) applying operation using a highest read voltage among the plurality of read voltage applying operations (Fig. 12C-F: WLn, WL_unsel, VreadK, VrA-G), to a word line potential higher (Fig. 12F: WLn, 1243) than a word line potential of the other word line setting operations (Fig. 12C-F: WLn, WL_unsel, 1223, 1224, 1233, 1234, 1243, 1244, 1253), and control the peripheral circuit (Fig. 1A: 122, 124, 128) such that word lines of the memory block (Fig. 7A: BLK0) have the set word line potential.
However, Lu fails to teach wherein during each of the plurality of word line setting operations, a voltage at one level is applied to a selected word line and unselected word lines.
Jia teaches wherein during each of the plurality of word line setting operations (Fig. 6A: 520), a voltage at one level (Fig. 6A: VREAD, T2-T3) is applied to a selected word line (Fig. 6A: 667) and unselected word lines (Fig. 6A: 665).
Jia discloses that applying a single voltage to all of the word lines prior to performing the read operation reduces the rate of temporary read errors that occur when the first read is done on a nonvolatile memory such as NAND flash after being in an idle state. Many readable bits are incorrectly counted as failed bits during this first read and slows down read times by having to reperform the read operations to get accurate failed bit counts. It would therefore improve up read schemes to apply this method to other read operations in flash memories.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Jia to the teachings of Lu to produce a method of reading memory cells by applying one voltage level to the selected and unselected word lines prior to performing the read operation on the cells on the selected word line.
Regarding Claim 10, Lu and Jia teach the limitations of Claim 9. Lu further teaches wherein the control logic (Fig. 1A: 110) sets a second specific word line setting operation (Fig. 12D: 1233) among the plurality of word line setting operations, which is performed just before a second specific read voltage applying operation (Fig. 12D: VrB, VrD, VrF) using a second highest read voltage (Fig. 12D: VrF) among the plurality of read voltage applying operations (Fig. 12C-F: VrA-G), to a word line potential (Fig. 12D: 1233 which is lower than the word line potential of the first specific word line setting operation (Fig. 12F: WLn, 1243) and is higher than a word line potential of the other word line setting operations (Fig. 12C: WLn, 1223) except the first specific word line setting operation and the second specific word line setting operation.
Regarding Claim 11, Lu and Jia teach the limitations of Claim 10. Lu further teaches wherein the peripheral circuit (Fig. 1A: 122, 124, 128) controls the word lines to have a first voltage level (Fig. 12E: 1243) in the first specific word line setting operation, and controls the word lines to have a second voltage level (Fig. 12C: 1224) in the other word line setting operations except the first specific word line setting operation (Fig. 12E: 1243) and the second specific word line setting operation (Fig. 12C: 1224), and
wherein the first voltage level (Fig. 12E: 1243) is a positive voltage level higher than zero volts (col 28 lines 8-9 “plot 1243 shows the reduced level being Vcgr=VrC”).
Regarding Claim 12, Lu and Jia teach the limitations of Claim 11. Lu further teaches wherein the peripheral circuit (Fig. 1A: 122, 124, 128) controls the word lines to have a third voltage level (Fig. 12D: 1233) in the second specific word line setting operation, and
wherein the third voltage level (Fig. 12D: 1233) is a positive voltage level higher than zero volts (col 27 lines 55-56 “1233 shows the reduced level being Vcgr=VrB”).
Regarding Claim 13, Lu and Jia teach the limitations of Claim 11. Lu further teaches wherein the peripheral circuit (Fig. 1A: 122, 124, 128) controls the word lines to have the second voltage level (Fig. 12C: 1224) before a first read voltage applying operation (Fig. 12C: WLn, VrE, VrA) among the plurality of read voltage applying operations (Fig. 12C-E: WLn, VrA-G) is performed.
Regarding Claim 14, Lu and Jia teach the limitations of Claim 11. Lu further teaches wherein the peripheral circuit (Fig. 1A: 122, 124, 128) controls the word lines to have the second voltage level (Fig. 12E: Vss) after a last read voltage (Fig. 12E: WLn, VrC, VrG) applying operation among the plurality of read voltage applying operations (Fig. 12C-E: WLn, VrA-G) is performed.
Regarding Independent Claim 15, Lu teaches a method of operating a memory device (Fig. 1A: 100), the method comprising:
performing a first word line setting operation (Fig. 12C: WLn, 1224, 1253) of controlling a plurality of word lines of a memory block to have a first voltage level (Fig. 12C: 1224);
performing a first read voltage (Fig. 12C: VrA, VrE) applying operation on a selected word line (Fig. 12C: WLn);
performing a second word line setting operation (Fig. 12D: WLn, 1233, 1253) of controlling the selected word line to have a second voltage level (Fig. 12D: 1233) after the first read voltage applying operation is performed;
performing a second read voltage applying operation (Fig. 12D: VrB, VrD, VrF) on the selected word line (Fig. 12D: WLn);
performing a third word line setting operation (Fig. 12E: WLn, 1243, 1253) of controlling the selected word (Fig. 12E: WLn) line to have a third voltage level after the second read voltage applying operation (Fig. 12D: VrB, VrD, VrF) is performed; and
performing a third read voltage applying operation (Fig. 12E: VrC, VrG) on the selected word line (Fig. 12E: WLn),
wherein the third voltage level (Fig. 12E: WLn, 1243) of the third word line setting operation performed just before the third read voltage applying operation (Fig. 12E: VrC, VrG) using a highest read voltage (Fig. 12E: VrG) among the first read voltage applying operation, the second read voltage applying operation, and the third read voltage applying operation is performed is higher than each of the first voltage level (Fig. 12C: WLn, 1224) and the second voltage level (Fig. 12D: WLn, 1234).
However, Lu fails to teach wherein during each of the plurality of word line setting operations, a voltage at one level is applied to a selected word line and unselected word lines.
Jia teaches wherein during each of the plurality of word line setting operations (Fig. 6A: 520), a voltage at one level (Fig. 6A: VREAD, T2-T3) is applied to a selected word line (Fig. 6A: 667) and unselected word lines (Fig. 6A: 665).
Jia discloses that applying a single voltage to all of the word lines prior to performing the read operation reduces the rate of temporary read errors that occur when the first read is done on a nonvolatile memory such as NAND flash after being in an idle state. Many readable bits are incorrectly counted as failed bits during this first read and slows down read times by having to reperform the read operations to get accurate failed bit counts. It would therefore improve up read schemes to apply this method to other read operations in flash memories.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Jia to the teachings of Lu to produce a method of reading memory cells by applying one voltage level to the selected and unselected word lines prior to performing the read operation on the cells on the selected word line.
Regarding Claim 16, Lu and Jia teach the limitations of Claim 15. Lu teaches wherein the third voltage level (Fig. 12E: 1243) is higher than zero volts (col 28 lines 8-9 “plot 1243 shows the reduced level being Vcgr=VrC”).
Regarding Claim 17, Lu and Jia teach the limitations of Claim 15. Lu further teaches wherein the second voltage level (Fig. 12D: 1233) of the second word line setting operation performed just before the second read voltage applying operation (Fig. 12D: WLn, VrB, VrD, VrF) using a second highest read voltage (Fig. 12D: VrF) among the first read voltage applying operation (Fig. 12C: WLn, VrA, VrE), the second read voltage applying operation (Fig. 12C: WLn, VrB, VrD, VrF), and the third read voltage applying operation (Fig. 12C: WLn, VrC, VrG) is performed is higher than the first voltage level (Fig. 12C: 1224) and is lower than the third voltage level (Fig. 12E: 1243).
Regarding Claim 18, Lu and Jia teach the limitations of Claim 17. Lu further teaches wherein the second voltage level (Fig. 12D: 1233) is higher than zero volts (col 27 lines 55-56 “1233 shows the reduced level being Vcgr=VrB”).
Regarding Claim 19, Lu and Jia teach the limitations of Claim 15. Lu further teaches wherein the first read voltage applying operation (Fig. 12C: WLn, VrA, VrE) is an operation for reading a least significant bit of memory cells connected to the selected word line, wherein the second read voltage applying operation (Fig. 12D: WLn, VrB, VrD, VrF) is an operation for reading a center significant bit of the memory cells, and wherein the third read voltage applying operation (Fig. 12E: WLn, VrC, VrF) is an operation for reading a most significant bit of the memory cells.
Regarding Claim 20, Lu and Jia teach the limitations of Claim 15. Lu further teaches wherein the first read voltage applying operation (Fig. 12C: WLn, VrA, VrE) is an operation for reading a most significant bit of memory cells connected to the selected word line, wherein the second read voltage applying operation (Fig. 12D: WLn, VrB, VrD, VrF) is an operation for reading a center significant bit of the memory cells, and wherein the third read voltage applying operation (Fig. 12E: WLn, VrC, VrF) is an operation for reading a least significant bit of the memory cells.
Regarding Claim 21, Lu and Jia teach the limitations of Claim 15. Lu further teaches comprising performing a fourth word line setting operation (Fig. 12E: Vss) of controlling the selected word line to have a fourth voltage level (Fig. 12E: Vss) after the performing of the third read voltage applying operation (Fig. 12E: VrC, VrG) on the selected word line (Fig. 12E: WLn),
wherein the fourth voltage (Fig. 12E: Vss) level is lower than the third voltage level (Fig 12E: 1243).
Response to Arguments
Applicant’s arguments, see pages 11-12 section III, filed January 23, 2026, with respect to claim 6 have been fully considered and are persuasive. The 35 U.S.C. 112(a) new matter rejection of the non-final FAOM mailed October 24, 2025 has been withdrawn.
Applicant’s arguments with respect to claims 1, 9, and 15 have been considered but are moot because the new ground of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JOSEPH FIDELIS STORMES/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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