Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The Office Action supersedes the Office Action dated 9/29/25. The response date will be reset from the day this new Office Action is mailed.
Claims 1--20 are pending in this application. Claims 1, 11 and 20 are independent.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The Information Disclosure Statements (IDS) submitted on 5/22/24 and 11/29/24 by the applicant have been received and fully considered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. §103 as being unpatentable over Scheuerlein (US – 2013/0135925) in view of Berger (US 10,699,761) and further in view of Gupta (US – 10,079,056).
Examiner’s Note:
A reference must be considered in its entirety, not in isolation.”— In re Wesslau, 353 F.2d 238.
“The test for obviousness is what the combined teachings of the references would have suggested to those of ordinary skill in the art.”
— In re Keller, 642 F.2d 413 (CCPA 1981).
Key Note for the Applicant to consider:
There is no legal requirement that: all limitations appear in one figure, or all limitations be disclosed in one paragraph.
This Office Action properly relies on the teachings of the references as a whole, not on a rigid, element-by-element figure overlay.
Also, The examiner used “the cited references are relied upon for their combined teachings as understood by a person of ordinary skill in the art. The Office Action does not require a one-to-one correspondence between individual claim limitations and a single figure or paragraph of any reference. Rather, the rejection properly relies on the collective disclosures of the references, which, when combined, render the claimed subject matter obvious under 35 U.S.C. §103.”
Regarding Independent Claim 1:
Claim 1 is rejected under 35 U.S.C. §103 as being unpatentable over Scheuerlein in view of Berger and further in view of Gupta.
Scheuerlein discloses a memory device comprising a memory cell including an access device and a variable resistance element, with a word line coupled to a gate of the access device. Scheuerlein further teaches that during read operations, a reduced word-line voltage is applied to avoid disturbing the resistive state, while during write operations, a higher programming voltage is applied (Scheuerlein, discussion of read/write biasing of resistive memory cells).
Berger discloses a gate driver circuit configured using PMOS and NMOS transistors to selectively couple different supply voltages to an output node depending on control signals. Berger teaches that an NMOS pass transistor naturally attenuates an applied voltage by its threshold voltage, while a PMOS device can pass a higher voltage without attenuation when enabled. Berger further discloses control logic that switches between such paths depending on an operational mode.
Gupta explicitly places this architecture in the context of MRAM cells with access transistors, and confirms that read operations use reduced word-line voltage while write operations use elevated voltage levels to ensure proper switching.
A person of ordinary skill in the art would have been motivated to combine Scheuerlein’s resistive memory biasing requirements with Berger’s CMOS driver circuitry to implement a gate driver that attenuates the word-line voltage during read and passes an unattenuated higher voltage during write, as claimed. Gupta confirms the suitability of this approach for MRAM cells. The combination yields predictable results and addresses a well-known reliability concern.
As for dependent Claims 2–10:
Claims 2–3: NMOS threshold attenuation and high-voltage devices are explicitly taught by Berger and are routine design choices for memory drivers handling elevated write voltages.
Claims 4–9: The detailed four-transistor PMOS/NMOS driver topology and control signals are directly disclosed in Berger; Scheuerlein supplies the memory context.
Claim 10: MRAM memory cells are explicitly taught by Gupta.
Regarding Independent Claim 11:
Claim 11 is rejected under 35 U.S.C. §103 as being unpatentable over Scheuerlein in view of Berger and further in view of Gupta.
Claim 11 extends the architecture of claim 1 to a memory array with column decoding and bit/source lines. Scheuerlein discloses resistive memory arrays with word lines, bit lines, source lines, and column decoding circuitry. Berger teaches that the same PMOS/NMOS gate driver structure used for word lines may be applied to other control lines, including column-related lines.
Gupta confirms that MRAM arrays employ both word-line and column-line drivers and that voltage scaling during read vs. write is required on multiple control paths.
Thus, applying the same attenuating/unattenuating gate driver architecture to an array-level word line in combination with column decoding circuitry would have been an obvious design choice to a person of ordinary skill in the art seeking uniform voltage control across the memory array..
As for dependent Claims 12–19:
Applying the same gate-driver architecture to column lines, including PMOS/NMOS transistor arrangements and control logic, is an obvious extension of Berger’s teachings and is confirmed by Gupta’s array-level MRAM discussion.
Regarding Independent Claim 20:
Claim 20 is rejected under 35 U.S.C. §103 as being unpatentable over Berger in view of Scheuerlein and Gupta.
Berger explicitly discloses a stand-alone gate driver circuit comprising PMOS and NMOS transistors arranged to selectively couple different supply voltages to an output node depending on enable and control signals. Berger teaches attenuation during one mode and direct coupling during another.
Scheuerlein and Gupta provide the functional motivation for such a driver in resistive memory systems: protecting memory states during read and enabling strong programming during write.
Accordingly, the gate driver circuit of claim 20 represents a direct abstraction of Berger’s driver, applied to the memory context taught by Scheuerlein and Gupta..
Citation of Relevant Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Applicants are directed to consider additional pertinent prior art included on the Notice of References Cited (PTOL 892) attached herewith.
Conclusion
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HIEN N. NGUYEN
Primary Examiner
Art Unit 2824
/HN/
January 23, 2026
/HIEN N NGUYEN/Primary Examiner, Art Unit 2824