DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 7-8, and 12-20 are rejected under 35 U.S.C. 102(a)(1) as anticipated by Kondo (US 2013/0300505 A1).
Regarding Claim 1: Kondo discloses an RF power amplifier device (FIG. 18, element 100; FIG. 1, FIG. 18; Para [0003]).
Kondo discloses a semiconductor substrate/chip (FIG. 1, element "Si (chip)"; FIG. 11, substrate/chip 10; Para [0016]).
Kondo discloses a differential amplifier circuit (FIG. 18, differential push-pull amplifier stage 105; FIG. 1, differential push-pull amplifier circuit comprising transistor pair 7A/7B; Para [0017]) located on the substrate (FIG. 11, 10), including a pair of differential input nodes (FIG. 1, gates receiving +Input and -Input; Para [0017]) and a pair of differential output nodes (FIG. 1, drains coupled to 1A, 1B; FIG. 18, drains of 107/108).
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Fig. 1 of Kondo annotated by the examiner for ease of reference.
Kondo discloses an input/interstage transformer (FIG. 18, transformer 102; FIG. 18, transformer 106) comprising a primary coil and a secondary coil, where the ends of the secondary coil are connected to the pair of differential input nodes of the differential amplifier (FIG. 18, secondary of 102/106 connected to inputs of 104/105), and an intermediate point/center tap of the secondary coil is AC grounded (FIG. 18, ground connection at center tap of secondary of transformer 102/106).
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Fig. 18 of Kondo annotated by the examiner for ease of reference.
Kondo discloses an output transformer (FIG. 18, transformer 110; FIG. 1/FIG. 2, primary metal wires 1A-1D) having a primary coil and a secondary coil, where the ends of the primary coil are connected to the pair of differential output nodes (drains of transistors 107/108; FIG. 1, 7A/7B drains), and an intermediate point/center tap of the primary coil is AC grounded (FIG. 18, Vdd node provided at center tap with AC decoupling to GND; FIG. 1, Vdd connection at center tap; Para [0017]).
Kondo discloses differential wire pairs connecting the secondary coil of the input transformer to the differential input nodes of the amplifier circuit (FIG. 1, wires connecting input ports to gates of 7A/7B; FIG. 4, input differential lines) and connecting the differential output nodes (drains) to the primary coil ends of the second transformer (FIG. 1, connections to 1A, 1B; FIG. 4, lower-layer cross wire 5F and wire connections; Para [0026]).
Kondo explicitly discloses that in plan view, the input signal lines/wires to the differential transistor gates form cross wires that intersect with each other (FIG. 2, FIG. 3, cross wires 8A-8D; FIG. 4, lower-layer cross wire 5E/5F; Para [0023], [0026]), while the other set of connecting wires (such as straight interconnects or non-crossing drain lines) do not intersect with each other (FIG. 1, parallel straight lines to primary slabs 1A-1D; FIG. 6).
Regarding Claim 18: Kondo discloses an RF power amplifier device (FIG. 1, FIG. 2, FIG. 18, element 100; Para [0003]).
Kondo discloses a semiconductor substrate/chip (FIG. 11, substrate 10; FIG. 1, "Si (chip)"; Para [0016]).
Kondo discloses a plurality of differential push-pull amplifier circuits/transistors (FIG. 1, 7A-7H; FIG. 2, 3A-3H; Para [0017], [0019]), each having an input node (gate) and an output node (drain).
Kondo discloses a signal distribution system/transformer circuit (FIG. 2, FIG. 3, FIG. 18; Para [0008], [0017]) that converts/distributes signals across an array of amplifier pairs (FIG. 2, pairs 3A/3B, 3C/3D), where intermediate supply/ground centers are provided (FIG. 2, Vdd/GND taps; Para [0017]) to drive differential inputs of selected pairs.
Kondo discloses an output distributed active-transformer (DAT) power combining circuit (FIG. 1, FIG. 2, primary wires 1A-1H and secondary coil 2; FIG. 6, Output/GND ports O1, O2; Para [0007], [0018]) configured to combine outputs from the multiple push-pull amplifiers into a single-ended output signal (FIG. 1, "Output"; FIG. 6, O1).
Kondo explicitly discloses primary and secondary wires configured in an annular shape (octagonal/quadrilateral) in plan view (FIG. 1, FIG. 2, FIG. 3, element 2 and 1A-1H; Para [0007], [0018]).
Kondo discloses that the push-pull amplifiers are arranged along the outer/inner circumference in a circumferential direction of the annular shape (FIG. 1, FIG. 2, amplifiers 3A-3H/7A-7H arranged around the perimeter; Para [0018]).
Kondo discloses adjacent ends of the slab conductors arranged sequentially along the annular ring (FIG. 2, ends of 1A, 1H, 1B, 1C; Para [0019]-[0020]).
Kondo discloses symmetrical cross wires connecting adjacent ends of the annular conductor structures to input gates of adjacent differential transistor pairs (FIG. 2, cross wire pairs 8A, 8B, 8C, 8D, 8E, 8F, 8G, 8H; Para [0020], [0023]).
Kondo explicitly shows that each crosswire pair consists of two wires that cross/intersect each other in plan view (FIG. 2, intersection of 8A and 8B, 8C and 8D, etc.; Para [0023]).
Regarding Claim 2: Kondo teaches that a portion of a magnetic flux generated by the second transformer is interlinked with the first transformer (Kondo discloses nested concentric annular primary/secondary coils (FIG. 2, outer primary 1A-1H, secondary coil 2, inner primary 1I-1L; FIG. 5(A)-(B)). In this closely coupled monolithic/integrated layout, magnetic flux generated by the output transformer coil naturally interlinks with the adjacent input/interstage transformer coil on the same chip (Para [0009], [0018]).
Regarding Claims 7, 12, 13, 14, 19, Kondo further teaches that the second transformer / power combining circuit is in or on the substrate (Kondo explicitly discloses that the output transformer / power combining circuit (1A-1D, coil 2) is fabricated on the same silicon chip/substrate (FIG. 1, "Si (chip)"; FIG. 5(D), "Sub"; FIG. 11, substrate 10; Para [0016], [0024]).
Regarding Claim 8, 15, 16, 17, 20 Kondo teaches that the power amplifier further comprises a module substrate on which the substrate is mounted, wherein the second transformer / power combining circuit is in or on the module substrate (Kondo explicitly discloses embodiments where the semiconductor chip (10) containing the transistors is mounted on a separate module/wiring substrate (17) (FIG. 12, FIG. 13, FIG. 14, module substrate 17), and the output transformer (11) is located directly on/in the module substrate (FIG. 12, FIG. 13, transformer 11 on module substrate 17; Para [0027]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3-6 and 9-11 are rejected under 35 U.S.C. 103 as unpatentable over Kondo in view of Tsai (US 9,077,310 B2).
Claims 3, 4, 5, 6, 9, 10, 11 requiring specific multi-stage single-ended or cascaded upstream/downstream amplifier configurations, Kondo shows multi-stage differential configurations (FIG. 18). Where explicit single-ended or specific interstage transformer coupling details require enhancement, Tsai serves as a secondary reference in the same field of endeavor (RF power amplifiers with transformer matching).
Regarding Claims 3 and 9 (Single-Ended Input Stage Driving First Transformer), Kondo teaches an amplification device with a substrate, differential amplifier circuit, and primary/secondary transformer structure (FIG. 1, FIG. 18).
Kondo, however, doesn’t teach a single-ended amplifier circuit in/on the substrate configured to output a single-ended signal, wherein one end of the primary coil of the first transformer is connected to an output node of the single-ended amplifier circuit, and another end of the primary coil is grounded.
Tsai teaches single-ended driver amplifier stages integrated on the same chip, where a single-ended output drives one end of a primary transformer coil while the opposite end of the primary coil is connected to ground/AC ground to perform single-ended to differential conversion (balun action).
It would have been obvious to a person of ordinary skill in the art to modify Kondo's input stage (FIG. 18, 101/102) to incorporate Tsai's single-ended driver stage connected to a single-ended driven primary coil with the other end grounded.
Tsai teaches that using a single-ended driver stage prior to a differential transformer matching network simplifies the external RF input interface (requiring only a single-ended input pin) while maintaining differential driving capability for the downstream power amplifier stages. It would have been obvious to a POSITA to combine this feature with Kondo to accept standard single-ended RF input signals.
Regarding Claims 4, 5, 6, 10, 11 (Cascaded Downstream / Upstream Differential Amplifier Stages & Upstream Transformer) Kondo discloses multi-stage cascaded differential amplifier circuits (FIG. 18, driver stage 104, power stage 105) with interstage coupling transformers (106) having AC-grounded center taps and crosswire differential routing.
However, in full structural combination by Kondo Specific full cascading of downstream/upstream differential stages (Claims 4, 5, 10, 11) and duplicating the exact crosswire/non-crosswire differential pair arrangement across a secondary upstream transformer (Claim 6) is not taught explicitly.
Tsai explicitly details multi-stage cascaded differential power amplifiers using sequential transformer-coupled differential stages (upstream driver stages and downstream power stages) with AC-grounded center taps at each interstage transformer.
It would have been obvious to a person of ordinary skill in the art to modify Kondo's multi-stage amplifier system (FIG. 18) by configuring each cascaded interstage coupling network (upstream and downstream) using the exact transformer and differential wire routing geometry taught by Kondo (FIG. 2, FIG. 4) and structured in multi-stage cascade as taught by Tsai.
The obvious benefit would be cascading differential gain stages to achieve higher total power gain and improved power-added efficiency (PAE), as explicitly taught by both Kondo (Para [0006]) and Tsai. Implementing symmetric crosswire phase inversion/matching at each interstage transformer ensures consistent differential signal balance and phase alignment across all stages of the power amplifier lineup.
Conclusion
The prior arts, Dinc et al. (US20220224295), Meharry (US20100007416), Visser (US4873502) and Oritz (US20160261235A1) made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached on (571) 272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
Prosecution Insights