DETAILED ACTION
This office action is in response to the application filed 5/22/2024.
Currently, claims 1-20 are pending.
Information Disclosure Statement
The IDS filed 5/29/2025 includes a reference which is an office action written entirely in a non-English language, and thus cannot be considered by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites the limitation “a plurality of contacts surrounded by the charge storage structure”. There is no mention of a charge storage layer anywhere else in the claims. Thus, it is not clear what is meant by “the charge storage structure”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 19 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kanda et al. (US 8,315,094).
Pertaining to claim 1, Kanda shows, with reference to FIG. 2A, a semiconductor device comprising:
a substrate (11) comprising a first region (hosting 15e) and a second region (hosting SGS, MC, SGD);
a well region (13) located in the first region and the second region of the substrate;
a transistor device (15e) located in the well region of the first region; and
a memory device (comprising SGS, MC, SGD) located in the well region of the second region,
wherein the well region is continuous between the transistor device and the memory device.
Pertaining to claim 20, Kanda shows a top surface of the well region continuously extends from the first region to the second region.
In an alternative interpretation, only a memory cell may be interpreted to be the memory device. In this case, Kanda shows a semiconductor device comprising:
a substrate (11) comprising a first region (hosting 15e) and a second region (hosting SGS, MC, SGD);
a well region (13) located in the first region and the second region of the substrate;
a transistor device (15e) located in the well region of the first region; and
a memory device (MC) located in the well region of the second region,
wherein the well region is continuous between the transistor device and the memory device (continuous under the devices).
Pertaining to claim 19, Kanda shows another transistor device (14e) located in the well region of the first region; and another memory device (adjacent MC) located in the well region of the second region, wherein the well region between the transistor device and the another transistor device is continuous, and the well between the memory device and the another memory device is continuous (continuous under the devices).
Allowable Subject Matter
Claims 2-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record, either singularly or in combination, does not disclose or suggest the semiconductor device as it is claimed in claim 1, wherein a first gate structure of the transistor device and a second gate structure of the memory device each comprise a middle part and a peripheral part, a first opening and a second opening are provided between the middle part and the peripheral part, and the middle part is located between the first opening and the second opening. Thus, claim 2 is found to contain allowable subject matter. Claims 3-17 depend on claim 2, and thus also contain allowable subject matter.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL M LUKE whose telephone number is (571)270-1569. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL LUKE/Primary Examiner, Art Unit 2896
