Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 8, 9 and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Giammello et al. (8,803,614), hereafter called GIAMMELLO.
Regarding claim 1, GIAMMELLO (Fig. 2) discloses an electric device comprising: a first transistor (TR1), a control terminal of the first transistor being configured to receive an input signal (IN1); a second transistor (TR2) coupled in series with the first transistor (TR1), a first terminal (emitter/tDC2) of the second transistor being configured to receive the input signal at a first node; a first inductor (L1) coupled between first transistor and the first node; and a second inductor (L2) coupled to a control terminal of the second transistor, wherein the first inductor and the second inductor are mutually coupled to each other with transformer (T1) coupling.
Regarding claim 4, further comprising: a third inductor (Lo) configured to receive a reference voltage signal (Vcc), wherein the second inductor (L2) is configured to receive a first bias voltage signal (VB1), and the second transistor (TR2) is coupled in series between the first inductor (L1) and the third inductor (Lo).
Regarding claim 8, GIAMMELLO (Fig. 2) discloses an electric device comprising: receiving an input signal (IN1) by each of a control terminal of a first transistor (TR1) and a first terminal (emitter/tDC2) of a second transistor (TR2); in response to the input signal, inducing a current signal flowing through a first inductor (L2) which is coupled to a control terminal of the second transistor (TR2); and generating a first output signal (OU2) at a second terminal (collector) of the second transistor (TR2).
Regarding claim 9, wherein inducing the current signal comprises: inducing the current signal by a second inductor (L1) which is coupled between the first transistor (TR1) and the second transistor (TR2).
Regarding claim 14, GIAMMELLO (Fig. 2) discloses an electric device comprising: a first transistor (TR1); a first inductor (L1), a first terminal of the first inductor (OU1) being coupled to a first terminal (collector) of the first transistor (TR1); a second transistor (TR2), a first terminal (emitter) of the second transistor (TR2) being coupled to a second terminal (tDC2) of the first inductor (L1); and a second inductor (L2) coupled to a control terminal of the second transistor (TR2), wherein the first inductor and the second inductor are mutually coupled to each other with transformer (T1) coupling.
Claim(s) 1, 2, 4, 8, 9 and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (20170237402), hereafter called KIM.
Regarding claim 1, KIM (Fig. 8) discloses a cascode amplifier comprising: a first transistor (M1), a control terminal of the first transistor being configured to receive an input signal via matching circuit; a second transistor (M2) coupled in series with the first transistor (M1), a first terminal (source) of the second transistor being configured to receive the input signal at a first node (via source of transistor (M2)); a first inductor (inductor between transistors (M1 and M2)) coupled between first transistor and the first node; and a second inductor (inductor connected to the gate of transistor (M2)) coupled to a control terminal of the second transistor, wherein the first inductor and the second inductor are mutually coupled to each other with transformer (TR1) coupling.
Regarding claim 2, further comprising: a third inductor (ZL1) and a fourth inductor (LS1) coupled in series with the first transistor and the second transistor, wherein the first transistor and the second transistor are coupled between the third inductor and the fourth inductor.
Regarding claim 4, further comprising: a third inductor (ZL1) configured to receive a reference voltage signal, wherein the second inductor is configured to receive a first bias voltage signal, and the second transistor is coupled in series between the first inductor and the third inductor.
Regarding claim 8, KIM (Fig. 8) discloses a cascode amplifier comprising: receiving an input signal (via matching circuit) by each of a control terminal of a first transistor (M1) and a first terminal (source) of a second transistor (M2); in response to the input signal, inducing a current signal flowing through a first inductor (no label) which is coupled to a control/gate terminal of the second transistor (M2); and generating a first output signal at a second terminal (drain terminal) of the second transistor (M2).
Regarding claim 9, wherein inducing the current signal comprises: inducing the current signal by a second inductor (no label) which is coupled between the first transistor (M1) and the second transistor (M2).
Regarding claim 14, KIM (Fig. 8) discloses a cascode amplifier comprising: a first transistor (M1); a first inductor (no label), a first terminal of the first inductor being coupled to a first terminal (drain) of the first transistor (M1); a second transistor (M2), a first terminal (source) of the second transistor (M2) being coupled to a second terminal of the first inductor (no label); and a second inductor (no label) coupled to a control/gate terminal of the second transistor (M2), wherein the first inductor and the second inductor are mutually coupled to each other with transformer (TR1) coupling.
Allowable Subject Matter
Claims 3, 5-7, 10-13, and 15-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, prior art(s) does not disclose the third inductor and the fourth inductor are mutually coupled to each other with transformer coupling.
Regarding claim 5, prior art(s) does not disclose a third transistor coupled in series between the third inductor and the second transistor, a control terminal of the third transistor being configured to receive a second bias voltage signal.
Regarding claim 6, prior art(s) does not disclose the first inductor comprises: a third inductor coupled to the first transistor, and configured to receive the reference voltage signal at a second node; and a fourth inductor coupled to the second transistor, and configured to receive the reference voltage signal at the second node.
Regarding claim 7, prior art(s) does not disclose a third inductor configured to receive a reference voltage signal; and a third transistor coupled in series between the third inductor and the first transistor, a control terminal of the third transistor being configured to receive a first bias voltage signal.
Regarding claim 10, prior art(s) does not disclose receiving a bias voltage signal and a reference voltage signal by the first inductor and the second inductor, respectively.
Regarding claims 11-13, prior art(s) does not disclose receiving a first bias voltage signal and a first reference voltage signal by a control terminal of a third transistor and a second inductor, respectively, wherein the second transistor, the second inductor and the third transistor are coupled in series.
Regarding claims 15-20, prior art(s) does not disclose the first inductor comprises: a third inductor coupled to the first transistor, and configured to receive a first reference voltage signal at a first node; and a fourth inductor coupled to the second transistor, and configured to receive the first reference voltage signal at the first node.
Conclusion
The prior arts made of record and not relied upon is considered pertinent to applicant's disclosure.
Kong et al. (11,205,998), Fig. 7, which is considered to be the closest prior art to the subject matters claimed, which can also be used.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Khanh V. Nguyen whose telephone number is (571) 272-1767. The examiner can normally be reached from 8:30 AM – 5:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JESSICA HAN can be reached on (571) 272-2078. The fax phone numbers for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHANH V NGUYEN/ Primary Examiner, Art Unit 2843
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