Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in response to Application filed 05/22/24. Claims 1 – 20 has been examined and is pending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Dropps US 9767318 B1.
Regarding claims 1, 11 and 20, Drops anticipates a computing system, comprising: one or more components configured to:
store patch metadata and patch code in a one-time-programmable (OTP) memory of the computing system (15:35 – 40, shows Using the OTP, storing update along with metadata in cache i.e. memory);
program, before a processor of the computing system is released from a reset, the patch metadata into a patch hardware of the computing system (29:10 – 12, shows resetting and updating and see 15:37 – 39, which shows update along with metadata);
copy, before the processor is released from the reset, the patch code from the OTP memory into a random access memory (RAM) of the computing system (15:35 – 40, shows local copy along with OTP and updating metadata and 20:1 – 10 shows utilizing RAM);
identify, based on the patch metadata, an access attempt issued by the processor to a bad instruction in a read-only memory (ROM) of the computing system, wherein the bad instruction is associated with ROM firmware (16:40 -48, shows preventing access as well as unauthorized determination, also see 5:23 – 28, for bad copies as well as failure); and
direct the access attempt to the patch code stored in the RAM, wherein the ROM firmware is patched based at least in part on the patch code (19:20 – 25, shows implementing Direct User access and also access protection).
Regarding claims 2 and 12, the computing system of claim 1, wherein the one or more components are configured to program the patch metadata into the patch hardware and copy the patch code into the RAM, before the processor is released from the reset, to enable the ROM patching to be operational before the processor is released from the reset (17:5 – 15, see copy as well as metadata and updated).
Regarding claims 3 and 13, the computing system of claim 1, wherein the one or more components are configured to program the patch metadata into the patch hardware and copy the patch code into the RAM, before the processor is released from the reset, to enable the ROM to be patched starting from a first instruction of a boot sequence (9:20 – 40, see sequence).
Regarding claims 4 and 14, the computing system of claim 1, wherein the patch metadata includes one or more of:
a bad base field to indicate an offset of a bad instruction from a base address of
the ROM that is to be patched, a bad length field to indicate a length of a number of bad instructions to be patched, a good base field to indicate an offset from a starting address of the RAM at which the patch code is to be copied, a good length field to indicate a size of the patch code, or a subsystem identifier to indicate the processor that is associated with the patch
code (16:40 -48, shows preventing access as well as unauthorized determination, also see 5:23 – 28, for bad copies as well as failure).
Regarding claims 5 and 15, the computing system of claim 4, wherein the one or more components are configured to:
copy the patch code into the RAM based at least in part on the good length field, and the good length field and the bad length field are in terms of a number of word (see 5:23 – 28, for bad copies as well as failure).
Regarding claims 6 and 16, the computing system of claim 4, wherein the one or more components are configured to:
identify the access attempt to the bad instruction based at least in part on a match
to the offset from the base address in the bad base field; and issue a fetch to the starting address indicated in the good base field in order to patch the ROM firmware with the patch code.
Regarding claims 7 and 17, the computing system of claim 1, wherein the patch code corresponds to an instruction to patch the bad instruction in the ROM (23:5 – 18, see offset).
Regarding claims 8 and 18, the computing system of claim 1, wherein the patch code corresponds to multiple instructions, and the bad instruction in the ROM is replaceable with the
multiple instructions (14:30 – 35, see ROM, EEPROM).
Regarding claims 9 and 19, the computing system of claim 1, wherein the one or more components are configured to program the patch metadata into the patch hardware and copy the patch code into the RAM based at least in part on the patch hardware exiting a low power
Mode (15:35 – 40, shows local copy along with OTP and updating metadata and 20:1 – 10 shows utilizing RAM).
Regarding claim 10, the computing system of claim 1, wherein the one or more components are configured to store one or more patch codes contiguously from a start of a predefined patch area in the OTP memory (15:35 – 40, shows Using the OTP, storing update along with metadata in cache i.e. memory).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Dahiya et al. US 20210319107 A1 also discloses patching utilizing an OTP with associated metadata in a similar configuration.
Correspondence Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Chuck Kendall whose telephone number is 571-272-3698. The examiner can normally be reached on 10:00 am - 6:30pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hyung Sough can be reached on 571-272-6799. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUCK O KENDALL/
Primary Examiner, Art Unit 2192
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