DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
OBJECTION TO DRAWINGS
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. In, Fig.2 (RIGHT SIDE) BLDC MOTOR 115 (fig.1) INCORRECTLY REFERENCED AS 125. CONTROL WAVEFORMS W1-WN (SEE CLAIM 1) not shown in applicant’s figs.1-4. a low loss high frequency sensing circuit 150 coupled to the logic control circuit (SEE CLAIM 1) not shown. Closest fig.2 shows a low loss high frequency sensing circuit 150 coupled to the MCU 125. TRANSISTOR (Pi) not shown. Transistor is referenced as Q1, Q3, Q5 (figs.2-3). SENSEFET Si (see claim 1) NOT SHOWN. FIGS.2-3 SHOWS SENSEFET as Q2, Q4, Q6. Si comprises: (SEE CLAIM 1) a gate terminal coupled to the logic control circuit not shown. Figs.2-3 shows SENSEFET Q2, Q4, Q6 gate terminal coupled to the driver 210 (or pre Driver 315 abc).
Signal modulation engine (claims 1, 3, 12, 15), space vector modulation engine (claim 3) not shown, instead SMU 145 (see spec., page 3, para. [0017]) sates signal modulation unit or SPWM unit. High frequency signal injection (claim 1 and spec., page 5, para. [0026] injecting sinusoidal or trapezoidal) not shown in figs.1-4. Transit from high frequency signal injection mode to steady state mode (claims 7, 18) not shown in figs.1-4. Claim 4, states “The motor driver package of claim 1, wherein the logic control circuit further comprises a feedback controller configured to generate an error signal wherein, in a steady-state mode, the signal modulation engine is configured to generate the N control waveforms based on the error signal independent of the sensing output. Fig.1 shows (MCU 125, fig.1) comprises the feedback controller 160. Generating Error signal not shown in figs.1-4. Sensing outputs (O1, O2, Oi… ON, see claim 10) not shown in figs,1-4. Fig. 4 shows sensing outputs as C51, C52 & C53. Appropriate corrections are required.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Objection to Specification
The disclosure is objected to because of the following informalities: The spec teaches (see spec., page 3, para [0017]) states “Based on a phase and/or frequency of the BLDC motor 115, for example, the processor 140 may execute control algorithms stored in the SMU 145 to control signals to the driver unit 130” is not clear. Applicant’s fig.1 shows memory 135 as a storage. In general Processor execute control algorithms stored in memory. Spec. (see page 7, para. [0034], relative to fig.2), states “phase information of the MCU 125 (is it phase information of the BLDC motor 115?) because BLDC motor 115 (fig.1) is incorrectly referenced as 125 (shown on right side of fig.2). Spec., (see page 9, para. [0044]) states “a speed and a phase of the MCU 125” (Is it a speed and a phase of the BLDC motor 115?). Throughout Spec., (see page 10, para. [0048]) states High frequency signal injection mode, but fails to teach what a High frequency signal injection mode mean? Applicant’s figs.1-4 does not show High frequency injection mode signal. Spec., (see page 10, para. [0053]) states “motor control signals are generated in steady state mode” is unclear as applicant’s spec. fails to teach what the steady state mode mean? Figs.1-4 does not show a steady state mode signal.
Claim Rejections – 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 and 10-18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As to claim 1, The phrase, “a signal modulation engine comprising a program of instructions, wherein the microcontroller unit is configured to execute the signal modulation engine to generate N control waveforms, W1, W2, Wi, WN, wherein Wi corresponds to the i-th phase and is received by the gate terminal of the Pi” is unclear as to a signal modulation engine comprising a program of instructions because in general, a processor 140 (see fig.1) execute a program of instructions from memory 135. SMU 145 is a space vector (signal) modulation unit (fig.1, see spec., page 3, para. [0017]) and therefore a signal modulation engine comprising a program of instructions is not clear.
As to claim 1, The phrase, “the logic control circuit is configured to determine a phase information as a function of the sensing output in a high frequency signal injection mode” is not clear as to the phase information (is it the position information of the BLDC motor 115?) and also not clear as to the high frequency signal injection mode. Throughout Spec., (see page 10, para. [0048]) states High frequency signal injection mode, but fails to teach what a High frequency signal injection mode mean? Applicant’s figs.1-4 does not show application of High frequency injection mode signal (quasi sinusoidal or trapezoidal signal, see spec., page 5, para’s [0026], and page 10, [0048]).
As to claim 4, states “The motor driver package of claim 1, wherein the logic control circuit further comprises a feedback controller configured to generate an error signal wherein, in a steady-state mode, the signal modulation engine is configured to generate the N control waveforms based on the error signal independent of the sensing output”.
Fig.1 shows (MCU 125, fig.1) comprises the feedback controller 160. Generating Error signal not shown in figs.1-4.
As to claims 7 and 18, the phrase, “Transit from high frequency signal injection mode to steady state mode” is not clear as said transition is not shown in figs.1-4.
As to claim 10, the phrase, “a logic control circuit coupled to the gate terminal of each power transistor P1, P2, , PN” is not clear as logic control 310 is coupled to the Pre Driver 315abc, and pre Driver 315 abc applies the gate signals to transistors Q1-Q6 (see fig.3).
As to claim 10, a low loss high frequency sensing circuit 150 coupled to the logic control circuit (SEE CLAIM 1) is not clear as it is not shown. Closest fig.2 shows a low loss high frequency sensing circuit 150 coupled to the MCU 125.
As to claim 12, the phrase, “The motor driver package of claim 10, wherein the logic control circuit comprises a microcontroller unit and a signal modulation engine comprising a program of instructions, wherein the microcontroller unit is configured to execute the signal modulation engine to generate the gate signal based on the sensing input, wherein the gate signal comprises a control waveform” is not clear as to a signal modulation engine comprising a program of instructions because in general, a processor 140 (see fig.1) execute a program of instructions from memory 135. SMU 145 is a space vector (signal) modulation unit (fig.1, see spec., page 3, para. [0017]) and therefore a signal modulation engine comprising a program of instructions is not clear.
Appropriate corrections and clarifications required.
Allowable Subject-Matter
Claims 1-18 are allowed.
Claims 1-18 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter: As to claim 1, (closest prior art, Prabhala et al., US 2019/0157994 A1) teaches (figs.1-13, para’s [0001]-[0002], [0031]) a system 10 (figs.1, 6, 8-9) for controlling a BLDC motor 22, wherein MCU 14 as an integrated circuit (see figs.1, 6, 8-9, para. [0038]) applies gate signals G_SX (G_S1 thru G_S6, see figs.3, 6-9, para’s [0050]-[0052]. Gate signals G_S1 to G_S2/G_S3 to G_S4/G_S5 to G_S6 are synchronous related signals, see fig.3) via gate driver 140 to transistors 210-220 of inverter circuit 18c and teaches said control of motor 22 based on current sensing via current sensing MOSFETS 210-220 (see para’s [0076]-[0077]) and provide plural current sense outputs 211, 213, 215, 217, 219, 221 to MCU 14 via signal conditioning 142 (fig.9) and also teaches sensing phase (position) of motor 22 via position sensors 146 (fig.9, para. [0056]) and invention decreases power losses (see para’s [0078]-[0079]).
However, as to claim 1, Prabhala et al. fails to teach the current output of the sense terminal of Si is a positive fraction of a current input at the source terminal of Si, wherein: the logic control circuit is configured to determine a phase information as a function of the sensing output in a high frequency signal injection mode; and, the logic control circuit, the gate driver circuit, and the low loss high frequency sensing circuit are integrated within a unified physical package.
As to claim 10, (closest prior art, Prabhala et al., US 2019/0157994 A1) teaches (figs.1-13, para’s [0001]-[0002], [0031]) a system 10 (figs.1, 6, 8-9) for controlling a BLDC motor 22, wherein MCU 14 as an integrated circuit (see figs.1, 6, 8-9, para. [0038]) applies gate signals G_SX (G_S1 thru G_S6, see figs.3, 6-9, para’s [0050]-[0052]. Gate signals G_S1 to G_S2/G_S3 to G_S4/G_S5 to G_S6 are synchronous related signals, see fig.3) via gate driver 140 to transistors 210-220 of inverter circuit 18c and teaches said control of motor 22 based on current sensing via current sensing MOSFETS 210-220 (see para’s [0076]-[0077]) and provide plural current sense outputs 211, 213, 215, 217, 219, 221 to MCU 14 via signal conditioning 142 (fig.9) and also teaches sensing phase (position) of motor 22 via position sensors 146 (fig.9, para. [0056]) and invention decreases power losses (see para’s [0078]-[0079]).
However, as to claim 10, Prabhala et al. fails to teach Oi is a positive fraction of the drain output current of Pi; in a high frequency signal injection mode, the logic control circuit is configured to generate the gate signal of each of the N phases as a function of the sensing output; and, the logic control circuit, the gate driver circuit, and the low loss high frequency sensing circuit are integrated within a unified physical package.
Claims 1-18 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
Formal requirements outstanding needs to be corrected and clarified (see Objection to drawings and specification and 35 USC 112 rejection).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTONY M PAUL whose telephone number is (571)270-1608. The examiner can normally be reached M-F 8 am to 4 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Eduardo Colon Santana can be reached at 571-272-2060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTONY M PAUL/
Primary Examiner of Art Unit 2846