DETAILED ACTION
This action is responsive to the following communications: the Application filed May 22, 2024, and Information Disclosure Statement filed on May 22, 2024 and October 10, 2024.
Claims 1-20 are pending. Claims 1, 10 and 19 are independent.
Information Disclosure Statement
Acknowledged is made of Application’s Information Disclosure Statement (IDS) Form PTO-1449 filed on May 22, 2024 and October 10, 2024. These IDS have been considered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over YOON et al. (US 2015/0303948) in view of Jung (US 10,373,691).
Regarding independent claim 1, YOON et al. disclose a memory device comprising: a memory cell array comprising a plurality of pages, wherein each page of the plurality of pages comprises a plurality of memory cells (figures 5 and 6); a page buffer comprising a plurality of buffer units corresponding to the plurality of memory cells of each page (221-11-221-m, figure 6), wherein each buffer unit of the plurality of buffer units comprises a cache latch and first to N-th latches (see para.[0067] discloses: Each page buffer may also function as a latch that temporarily stores sensed and amplified, i.e. data read from the memory cell array 210), and N is an integer greater than or equal to 2 (see figure 6); and a control logic (260, figure 5) configured to control a first read operation with respect to a first page of the plurality of pages (see figure 13 below, also, see para.[0008] discloses: he method includes a first decoding operation including reading first hard decision data from the non-volatile memory device using a first hard decision read level and performing decoding using the first hard decision data; a second decoding operation including reading first soft decision data from the non-volatile memory device when the decoding fails in the first decoding operation and performing decoding using the first soft decision;) , wherein the first read operation stores first hard decision data in the page buffer based on a normal read level (figure 13 below: New HD Data based on VHD2) and stores first soft decision data in the page buffer based on an offset level (see figure 15A shows: first soft decision data is based on an offset read level from the first page),
However, Yoon et al. are silent with respect to output the first hard decision data to a memory controller after a second read operation with respect to a second page of the plurality of pages has started, wherein the second read operation is started in response to a first command that requests read of the second page, and output the first soft decision data to the memory controller in response to a second command from the memory controller while the second read operation is being performed.
Jung discloses output the first hard decision data (out, figure 12 below) to a memory controller (160, figure 2) after a second read operation with respect to a second page of the plurality of pages has started (figures and figure 6 below). Noted: after controls read the page then controls read second page and so on), wherein the second read operation is started in response to a first command that requests read of the second page (s210, figure 12 below), and output the first soft decision data (out, figure 12 below) to the memory controller in response to a second command from the memory controller while the second read operation is being performed (see comment above, figure 6 below).
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Since YOON et al. and Jung are both from the same field of endeavor, the purpose disclosed by Jung would have been recognized in the pertinent art of YOON et al.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of YOON et al. to teaching of Jung for purpose of using ECC circuit to correct the error bit to provided hard decision data.
Regarding claim 2, the combination of YOON et al. and Jung disclose the limitation of claim 1.
YOON et al. further disclose wherein the first soft decision data is compressed in the memory device, and the compressed first soft decision data has a smaller size than the first hard decision data (see figures 13 and 15 above).
Regarding independent claim 19. A memory system comprising: a memory device comprising a page buffer, the page buffer configured to store data read from a page, wherein the page buffer comprises a plurality of buffer units corresponding to a plurality of memory cells, and each buffer unit of the plurality of buffer units comprises a first latch, a second latch, a third latch, and a cache latch; and a memory controller configured to: receive hard decision data based on a normal read level and receive soft decision data based on an offset level, wherein the hard decision data and the soft decision data are read from the page; control the memory device to sequentially perform a first read operation with respect to a first page and a second read operation with respect to a second page; in response to outputting a first command to the memory device, receive first hard decision data from the memory device after the second read operation has started, the first hard decision data read by the first read operation; and in response to outputting a second command to the memory device while the second read operation is being performed, receive first soft decision data from the memory device before the second read operation is completed, the first soft decision data read by the first read operation (see rejection of claim 1).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over YOON et al. (US 2015/0303948) in view of Jung (US 10,373,691) further in view PARK (US 2023/0402071).
Regarding claim 3, the combination of YOON et al. and Jung disclose the limitation of claim 1.
However, YOON et al. are silent with respect to wherein the first hard decision data is stored in the first latch, and the first soft decision data is stored in the second latch,
PARK discloses wherein the first hard decision data is stored in the first latch, and the first soft decision data is stored in the second latch (see para.[0037] discloses: The plurality of data latches can include a first data latch configured to store the first hard decision data entry read from the first memory cell; and a second data latch configured to store the first soft decision data entry read from the first memory cell)
Jung discloses wherein the control logic is configured to output the first hard decision data stored in the cache latch to the memory controller after dumping the first hard decision data stored in the first latch to the cache latch, and dumping the first hard decision data is performed in response to the first command (see figure 12 below).
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Since YOON et al., Jung and PARK are from the same field of endeavor, the purpose disclosed by Jung AND PARK would have been recognized in the pertinent art of YOON et al.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of YOON et al. to teaching of Jung and PARK for purpose of using ECC circuit to correct the error bit to provided hard decision data.
Allowable Subject Matter
Claims 4-9 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claimed limitation of wherein N is an integer greater than or equal to 3, wherein the control logic is configured to dump the first soft decision data stored in the second latch to the third latch in response to the first command, and wherein the first soft decision data stored in the third latch is dumped to the cache latch in response to the second command, and the first soft decision data stored in the cache latch is output to the memory controller after the first soft decision data stored in the third latch is dumped to the cache latch in combination with the other limitations thereof as is recited in the claim. Claims 5-9 depend on claim 4.
Regarding claim 20, the prior art made of record and considered pertinent to applicant’s disclosure does not teach the claim limitation of a development section developing a voltage of the sensing node of each buffer unit, and a sensing section sensing a voltage of the sensing node of each buffer unit, and wherein the memory device is configured to: dump the first hard decision data stored in the first latch to the cache latch; output the first hard decision data stored in the cache latch to the memory controller; in response to receiving the first command, dump the first soft decision data stored in the second latch to the third latch while performing the second read operation; dump the first soft decision data stored in the third latch to the cache latch during a dump-allowed section, the dump-allowed section corresponding to a portion of the precharge section; and in response to receiving the second command, output the first soft decision data stored in the cache latch to the memory controller in combination with the other limitations thereof as is recited in the claim.
Claims 10-18 are allowed.
Regarding independent claim 18, the prior art does not teach of suggest the claimed invention having “the first hard decision data after dumping the first hard decision data to a cache latch of each buffer unit of the plurality of buffer units, dumping the first hard decision data being performed in response to receiving the first command; receiving a second command from the memory controller while a second read operation with respect to the second page is being performed; in response to receiving the second command, dumping the first soft decision data to the cache latch during a dump-allowed section, the dump-allowed section being defined in the second read operation; and outputting, to the memory controller, the first soft decision data that is dumped to the cache latch”, in combination of other limitations thereof as recited in the claim.
Regarding claims 11-18, the claims have been found allowable due to their dependencies to claim 10 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MINH D DINH whose telephone number is (571)270-5375. The examiner can normally be reached Monday to Friday 8:00am 5:00pm.
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/MINH D DINH/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827