DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-5, 8-9, and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Karimi et al. (US 2023/0072039).
Regarding claim 1, Karimi discloses, system and method for error correction coding architecture in figures 5B and 6 that teaches encoding plurality of info bits into coded bits using a zipper code associated w/ a first & second mapping function (maps 590, 592) (see at least associated paras. 0084-0092), zipper code associated with a real buffer (580) and first & second virtual buffers (560, 570) each comprising a plurality of sections (FIG. 6, see columns and rows), the buffers forming a codeword component (see "codeword" and "codewords" throughout '039 disclosure), the real buffer is for receiving the info bits (see para. 0088, 0091, FIGs. 5B & 6), wherein the mapping functions are for mapping each group of c bits in each section of the real buffer to c mapped bits in first & second subsequent sections of the first & second virtual buffers respectively (0088, 0091, FIGs. 5B & 6), where the c mapped bits in the first and/or second virtual buffers are in different sections (see figures 5B&6 and associated paras 0088, 0092).
Regarding claim 4, Karimi further teaches C=3 (see claim 5).
Regarding claim 5, Karimi discloses, system and method for error correction coding architecture in figures 5B and 6 that teaches encoding plurality of info bits into coded bits using a zipper code associated w/ a first & second mapping function (maps 590, 592) (see at least associated paras. 0084-0092), zipper code associated with a real buffer (580) and first & second virtual buffers (560, 570) each comprising a plurality of sections (FIG. 6, see columns and rows), the buffers forming a codeword component (see "codeword" and "codewords" throughout '039 disclosure), the real buffer is for receiving the info bits (see para. 0088, 0091, FIGs. 5B & 6), wherein the mapping functions are for mapping each group of c bits in each section of the real buffer to c mapped bits in first & second subsequent sections of the first & second virtual buffers respectively (0088, 0091, FIGs. 5B & 6), where the c mapped bits in the first and/or second virtual buffers are in different sections (see figures 5B&6 and associated paras 0088, 0092).
Regarding claim 8, Karimi further teaches C=3 (see claim 5).
Regarding claim 9, Karimi discloses, system and method for error correction coding architecture in figures 5B and 6 that teaches encoding plurality of info bits into coded bits using a zipper code associated w/ a first & second mapping function (maps 590, 592) (see at least associated paras. 0084-0092), zipper code associated with a real buffer (580) and first & second virtual buffers (560, 570) each comprising a plurality of sections (FIG. 6, see columns and rows), the buffers forming a codeword component (see "codeword" and "codewords" throughout '039 disclosure), the real buffer is for receiving the info bits (see para. 0088, 0091, FIGs. 5B & 6), wherein the mapping functions are for mapping each group of c bits in each section of the real buffer to c mapped bits in first & second subsequent sections of the first & second virtual buffers respectively (0088, 0091, FIGs. 5B & 6), where the c mapped bits in the first and/or second virtual buffers are in different sections (see figures 5B&6 and associated paras 0088, 0092).
Regarding claim 12, Karimi further teaches C=3 (see claim 5).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior arts of, considered individually or/and in combination, fail to fairly teach or suggest objected features, such as: the bit positions of the bits in the section of the real buffer, the bit positions of the corresponding mapped bits in any one of the one or more first subsequent sections of the first virtual buffer, and the bit positions of the corresponding mapped bits in any one of the one or more second subsequent sections of the second virtual buffer only have one bit position in common.
Claim 3 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior arts of, considered individually or/and in combination, fail to fairly teach or suggest objected features, such as: wherein, when the bits of each section of the first virtual buffer are indexed from 1 to m (m > 1 is an integer), the bits of each section of the second virtual buffer are indexed from m+1 to 2m, and the bits of each section of the real buffer are indexed from 2m+1 to 3m, the first mapping function Ꝋ1 maps j-th bit (j = 2m+1, ..., 3m) of i-th row of the real buffer to j1-th bit of i1-th row of the first virtual buffer, and
PNG
media_image1.png
93
729
media_image1.png
Greyscale
where [x] is a function returning a smallest integer that is greater than or equal to x, [y] is a function returning a greatest integer that is smaller than y, and a % b represents a modulo function returning a remainder of a divided by b, and the second mapping function Ꝋ2 maps the j-th bit of the i-th row of the real buffer to j2-th bit of i2-th row of the second virtual buffer,
and
PNG
media_image2.png
21
106
media_image2.png
Greyscale
(i,j) = i +
PNG
media_image3.png
54
93
media_image3.png
Greyscale
+ 1, (j - m).
Claim 6 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior arts of, considered individually or/and in combination, fail to fairly teach or suggest objected features, such as: the bit positions of the bits in the section of the real buffer, the bit positions of the corresponding mapped bits in any one of the one or more first subsequent sections of the first virtual buffer, and the bit positions of the corresponding mapped bits in any one of the one or more second subsequent sections of the second virtual buffer only have one bit position in common.
Claim 7 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior arts of, considered individually or/and in combination, fail to fairly teach or suggest objected features, such as: wherein, when the bits of each section of the first virtual buffer are indexed from 1 to m (m > 1 is an integer), the bits of each section of the second virtual buffer are indexed from m+1 to 2m, and the bits of each section of the real buffer are indexed from 2m+1 to 3m, the first mapping function Ꝋ1 maps j-th bit (j = 2m+1, ..., 3m) of i-th row of the real buffer to j1-th bit of i1-th row of the first virtual buffer, and
PNG
media_image1.png
93
729
media_image1.png
Greyscale
where [x] is a function returning a smallest integer that is greater than or equal to x, [y] is a function returning a greatest integer that is smaller than y, and a % b represents a modulo function returning a remainder of a divided by b, and the second mapping function Ꝋ2 maps the j-th bit of the i-th row of the real buffer to j2-th bit of i2-th row of the second virtual buffer,
and
PNG
media_image2.png
21
106
media_image2.png
Greyscale
(i,j) = i +
PNG
media_image3.png
54
93
media_image3.png
Greyscale
+ 1, (j - m).
Claim 10 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior arts of, considered individually or/and in combination, fail to fairly teach or suggest objected features, such as: the bit positions of the bits in the section of the real buffer, the bit positions of the corresponding mapped bits in any one of the one or more first subsequent sections of the first virtual buffer, and the bit positions of the corresponding mapped bits in any one of the one or more second subsequent sections of the second virtual buffer only have one bit position in common.
Claim 11 is objected to as being dependent upon a rejected base claim, but it would be considered for allowable if it is rewritten in independent form including all of the limitations of the base claim and any intervening claims. Closest prior arts of, considered individually or/and in combination, fail to fairly teach or suggest objected features, such as: wherein, when the bits of each section of the first virtual buffer are indexed from 1 to m (m > 1 is an integer), the bits of each section of the second virtual buffer are indexed from m+1 to 2m, and the bits of each section of the real buffer are indexed from 2m+1 to 3m, the first mapping function Ꝋ1 maps j-th bit (j = 2m+1, ..., 3m) of i-th row of the real buffer to j1-th bit of i1-th row of the first virtual buffer, and
PNG
media_image1.png
93
729
media_image1.png
Greyscale
where [x] is a function returning a smallest integer that is greater than or equal to x, [y] is a function returning a greatest integer that is smaller than y, and a % b represents a modulo function returning a remainder of a divided by b, and the second mapping function Ꝋ2 maps the j-th bit of the i-th row of the real buffer to j2-th bit of i2-th row of the second virtual buffer,
and
PNG
media_image2.png
21
106
media_image2.png
Greyscale
(i,j) = i +
PNG
media_image3.png
54
93
media_image3.png
Greyscale
+ 1, (j - m).
Allowable Subject Matter
Claims 13-21 are allowable.
The following is a statement of reasons for the indication of allowable subject matter: Claim 13 is allowed over the closest prior art of record, Karimi et at. (US 2023/0072039). The closest prior art of record, Karimi et at teaches: decoding (figures 5A and 5B and 6 and at least associated para. 087,088,089,0106)) a plurality of coded bits into a plurality of information bits using a zipper code associated with a first mapping function (590) and a second mapping function (592); wherein the zipper code is associated with a real buffer (580), a first virtual buffer (560), and a second virtual buffer (570), each comprising a plurality of sections (see figure 6, rows and columns); wherein each section of the real buffer(580), a corresponding section of the first virtual buffer (560), and a corresponding section of the second virtual buffer (570) form a codeword of a component code; wherein the real buffer is for receiving the plurality of coded bits into the plurality of sections thereof; wherein the first mapping function (590) and the second mapping function (592) are for mapping bits in each section of the real buffer (580) to a plurality of first subsequent sections of the first virtual buffer (560) and to bits in one or more second subsequent sections of the second virtual buffer (570), respectively. However, the closest prior art of record, Karimi considered individually or in combination, fails to fairly teach or suggest invented features, which is: wherein said decoding the plurality of coded bits comprises: determining that a syndrome of a first codeword is nonzero, the first codeword comprising a first one of the plurality of sections of the real buffer, and corresponding to plurality of second codewords comprising bits mapped from the bits of the first one of the plurality of sections of the real buffer, calculating syndromes of the plurality of second codewords, determining values of a plurality of variables, each of the plurality of variables corresponding to one of the plurality of second codewords, and having a value of binary zero if the syndrome of the corresponding second codeword is zero or a value of binary one if the syndrome of the corresponding second codeword is nonzero, and correcting a plurality of bits of the first one of the plurality of sections of the real buffer by determining values thereof based on the values of the plurality of variables”, structurally and functionally interconnected with other limitations in the manner as cited in the claim and dependent claims 14-15.
Claim 16 is allowed over the closest prior art of record, Karimi et at. (US 2023/0072039). The closest prior art of record, Karimi et at teaches: decoding (figures 5A and 5B and 6 and at least associated para. 087,088,089,0106)) a plurality of coded bits into a plurality of information bits using a zipper code associated with a first mapping function (590) and a second mapping function (592); wherein the zipper code is associated with a real buffer (580), a first virtual buffer (560), and a second virtual buffer (570), each comprising a plurality of sections (see figure 6, rows and columns); wherein each section of the real buffer(580), a corresponding section of the first virtual buffer (560), and a corresponding section of the second virtual buffer (570) form a codeword of a component code; wherein the real buffer is for receiving the plurality of coded bits into the plurality of sections thereof; wherein the first mapping function (590) and the second mapping function (592) are for mapping bits in each section of the real buffer (580) to a plurality of first subsequent sections of the first virtual buffer (560) and to bits in one or more second subsequent sections of the second virtual buffer (570), respectively. However, the closest prior art of record, Karimi considered individually or in combination, fails to fairly teach or suggest invented features, which is: wherein said decoding the plurality of coded bits comprises: determining that a syndrome of a first codeword is nonzero, the first codeword comprising a first one of the plurality of sections of the real buffer, and corresponding to plurality of second codewords comprising bits mapped from the bits of the first one of the plurality of sections of the real buffer, calculating syndromes of the plurality of second codewords, determining values of a plurality of variables, each of the plurality of variables corresponding to one of the plurality of second codewords, and having a value of binary zero if the syndrome of the corresponding second codeword is zero or a value of binary one if the syndrome of the corresponding second codeword is nonzero, and correcting a plurality of bits of the first one of the plurality of sections of the real buffer by determining values thereof based on the values of the plurality of variables”, structurally and functionally interconnected with other limitations in the manner as cited in the claim and dependent claims 17-18).
Claim 19 is allowed over the closest prior art of record, Karimi et at. (US 2023/0072039). The closest prior art of record, Karimi et at teaches: decoding (figures 5A and 5B and 6 and at least associated para. 087,088,089,0106)) a plurality of coded bits into a plurality of information bits using a zipper code associated with a first mapping function (590) and a second mapping function (592); wherein the zipper code is associated with a real buffer (580), a first virtual buffer (560), and a second virtual buffer (570), each comprising a plurality of sections (see figure 6, rows and columns); wherein each section of the real buffer(580), a corresponding section of the first virtual buffer (560), and a corresponding section of the second virtual buffer (570) form a codeword of a component code; wherein the real buffer is for receiving the plurality of coded bits into the plurality of sections thereof; wherein the first mapping function (590) and the second mapping function (592) are for mapping bits in each section of the real buffer (580) to a plurality of first subsequent sections of the first virtual buffer (560) and to bits in one or more second subsequent sections of the second virtual buffer (570), respectively. However, the closest prior art of record, Karimi considered individually or in combination, fails to fairly teach or suggest invented features, which is: wherein said decoding the plurality of coded bits comprises: determining that a syndrome of a first codeword is nonzero, the first codeword comprising a first one of the plurality of sections of the real buffer, and corresponding to plurality of second codewords comprising bits mapped from the bits of the first one of the plurality of sections of the real buffer, calculating syndromes of the plurality of second codewords, determining values of a plurality of variables, each of the plurality of variables corresponding to one of the plurality of second codewords, and having a value of binary zero if the syndrome of the corresponding second codeword is zero or a value of binary one if the syndrome of the corresponding second codeword is nonzero, and correcting a plurality of bits of the first one of the plurality of sections of the real buffer by determining values thereof based on the values of the plurality of variables”, structurally and functionally interconnected with other limitations in the manner as cited in the claim and dependent claims 20-21.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAM T MAI whose telephone number is (571)272-1807. The examiner can normally be reached Monday-Friday 6am-2pm eastern time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dameon Levi can be reached at 571 272-2105. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LAM T MAI/Primary Examiner, Art Unit 2845