DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
Paragraph 21, Line 15 – “complimentary” should be “complementary”.
Appropriate correction is required.
Claim Objections
Claims 2, 9 and 13 are objected to because of the following informalities:
Claim 2 line 2, “ complimentary” should be – complementary--.
Claim 9 line 6, “ complimentary” should be – complementary--.
Claim 13 line 6, “ complimentary” should be – complementary--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Mao et al., US Patent 9516723 (Mao) in view Inderjit Singh Dhanjal Publication title “Filter Circuits”, 2017 (Inderjit), and in further view of He et al., CN Publication 106208726 (He).
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Regarding claim 1, Mao discloses a circuit (i.e., 30 ) (fig. 6) for stepping down an alternating current (AC) voltage from an input voltage (i.e., 32) (Fig. 6) to an output voltage (For example see output voltage between nodes 386, 388) (Fig. 6), the circuit (i.e., 30 ) (fig. 6) comprising:
an input (i.e., In ) (fig. 6) configured to couple to a voltage source for providing the input voltage as an AC signal to the circuit (i.e., 30 ) (fig. 6);
a first capacitor (i.e., 364) (Fig. 6) in parallel with the input (i.e., 32) (Fig. 6) and an output (output voltage between nodes 386, 388) (Fig. 6);
a first inductor (i.e., 362) (fig. 6) in series with the input (i.e., 32 ) (fig. 6) and the output (output voltage between nodes 386, 388) (Fig. 6);
a first switch (i.e., 342) (fig. 6) in series with the input (i.e., 32) (fig. 6) and the output (i.e., 386,388) (fig. 6) and a second switch (i.e., 344) (fig. 6), wherein the output voltage (i.e., 386, 388) (fig. 6) of the circuit (i.e., 30) (fig. 6) provided to the output is an AC signal that is less than or equal to the input AC signal based on a duty cycle of the first switch (i.e., 342) (fig. 6).
Mao, as applied above, fail to disclose a second capacitor in parallel with the input and an output and a second inductor in series with the input and the output.
Regarding the second capacitor in parallel with the input and an output, Mao, as applied above, discloses a filter with a capacitor in parallel for smoothing the voltage output but fail to disclose a second capacitor in parallel with the input and an output.
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Inderjit, in the same field of endeavor discloses several topologies of filters comprising a CLC filter, wherein in the CLC filter includes a first and second capacitor in parallel in order to provide a filter configuration used for smoothing the voltage output.
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Regarding the second inductor in series with the input and the output. He, in the same field of endeavor, discloses a input filter inductor (i.e., L) (Fig. 1) in series with the input and the output coupled to the AC source in order to smooth sudden changes at the input of the system.
Therefore, It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have optionally a second capacitor in parallel with the input and an output as a topology of a CLC filter in Mao, as taught by Inderjit, for smoothing the voltage output and further include a second inductor in series with the input and the output in Mao, as taught by He, in order to smooth sudden changes at the input of the system.
Regarding claim 2, Mao discloses a wherein the first switch (i.e., 342) (fig. 6) and second switch (i.e., 344) (fig. 6) are complimentary.
Claims 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Mao et al., US Patent 9516723 (Mao) in view Inderjit Singh Dhanjal Publication title “Filter Circuits”, 2017 (Inderjit) in further view of He et al., CN Publication 106208726 (He) and in further view of A.K. Chattopadhyay, Chapter 18 - AC–AC Converters, Power Electronics Handbook (Third Edition), Butterworth-Heinemann, 2011, Pages 487-521 ( Chattopadhyay).
Regarding claim 3, Mao in view of Inderjit in further view of He, as applied in linking claims, discloses the claimed invention but fail to disclose wherein the first switch and second switch are thyristors that perform switching at a frequency of 10 kilohertz (kHz), such that the first switch and second switch have a total duty cycle length of 100 microseconds.
Chattopadhyay, in the same field of endeavor discloses, wherein the use of thyristors (for example see Fig. 18.1) that perform switching at a frequency of 10 kilohertz (kHz) as alternative for the transistors in a AC-AC converter (for example a AC Chopper).
Therefore, It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have optionally use of thyristors that perform switching at a frequency of 10 kilohertz (kHz) in Mao in view of Inderjit and He, as taught by Chattopadhyay, as a substitution for transistors in a AC- AC converter (for example a AC Chopper).
Regarding claim 4, Mao in view of Inderjit , He and Chattopadhyay, as applied above, discloses the claimed invention, wherein Moa discloses the input voltage has a frequency of 60 Hz and the output voltage has a frequency of 60Hz.
Regarding claim 5, Mao in view of Inderjit , He and Chattopadhyay, as applied above, discloses the claimed invention, more particularly Chattopadhyay discloses the output voltage is characterized by the input voltage multiplied by , wherein is the duty cycle of the first switch (for example see equation 18.5).
Claims 8 is rejected under 35 U.S.C. 103 as being unpatentable over Mao et al., US Patent 9516723 (Mao) in view Inderjit Singh Dhanjal Publication title “Filter Circuits”, 2017 (Inderjit) in further view of He et al., CN Publication 106208726 (He), in further view of A.K. Chattopadhyay, Chapter 18 - AC–AC Converters, Power Electronics Handbook (Third Edition), Butterworth-Heinemann, 2011, Pages 487-521 ( Chattopadhyay) and in further view of Li et al., WO Publication 2017024995 (Li).
Regarding claim 8, Mao in view of Inderjit , He and Chattopadhyay, as applied above, discloses the claimed invention, more particularly Mao discloses the use of high current inductors. However, Mao in view of Inderjit , He and Chattopadhyay, fail to disclose the first and second capacitors are be ceramic, electrolytic, polymer, film, or variable capacitors.
Li, in the same field of endeavor discloses, discloses the use of film capacitor in order to reduce losses.
Therefore, It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have optionally provide a first and second capacitors of ceramic, electrolytic, polymer, film, or variable capacitors in Mao in view of Inderjit, He and Chattopadhyay, as taught by Li, as to provide a capacitor which reduce losses.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kusumoto et al., US Patent 6326772 (Kusumoto) in view of He et al., CN Publication 106208726 (He).
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Regarding claim 10, Kusumoto discloses a circuit (i.e., 30 ) (fig. 6) for stepping down an alternating current (AC) voltage comprising:
a first input (i.e., 3a) (fig. 11A) having a negative terminal coupled to a ground pin (i.e., G) (fig. 11A); wherein the first input (i.e., 3a) (fig. 47) is configured to couple to a voltage source (i.e., 211) (fig. 11A) for providing input voltage as an AC signal to the circuit; a first switch (i.e., 26) (fig. 47) having a second terminal coupled to a first node (i.e., 3c) (fig. 47); a second switch (i.e., 66) (fig. 47) having a first terminal coupled to the first node (i.e., 3c) (fig. 47) and a second terminal coupled to the ground pin (i.e., G) (fig. 11A); a second inductor (i.e., 28) (fig. 47) having a first terminal coupled to the first node (i.e., 3c) (fig. 47) and a second terminal coupled to a second node (i.e., 3e) (fig. 47); a second capacitor (i.e., 29) (fig. 47) having a first terminal coupled to the second node (i.e., 3e) (fig. 47) and a second terminal coupled to the ground pin (i.e., G) (fig. 47);a positive output terminal coupled to the second node (i.e., 3d) (fig. 47); a negative output terminal coupled to the ground pin (i.e., G) (fig. 11A).
Kusumoto fail to disclose a first input (i.e., 3a) (fig. 11A) having a positive terminal coupled to a first terminal of a first inductor and the first switch (i.e., 26) (fig. 47) having a first terminal coupled to a second terminal of the first inductor.
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He, in the same field of endeavor, discloses a first input (i.e., In) (Fig. 1) a having a positive terminal coupled to a first terminal of a first inductor (i.e., L) (Fig. 1) and the first switch (i.e., S3) (fig. 1) having a first terminal coupled to a second terminal of the first inductor (i.e., L) (Fig. 1) in order to smooth sudden changes at the input of the system.
Therefore, It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have optionally include a first input (i.e., In) (Fig. 1) a having a positive terminal coupled to a first terminal of a first inductor (i.e., L) (Fig. 1) and the first switch (i.e., S3) (fig. 1) having a first terminal coupled to a second terminal of the first inductor (i.e., L) (Fig. 1) in Kusumoto, as taught by He, in order to smooth sudden changes at the input of the system.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kusumoto et al., US Patent 6326772 (Kusumoto) in view of He et al., CN Publication 106208726 (He) and in further view of A.K. Chattopadhyay, Chapter 18 - AC–AC Converters, Power Electronics Handbook (Third Edition), Butterworth-Heinemann, 2011, Pages 487-521 ( Chattopadhyay).
Regarding claim 11, Kusumoto in view of He, as applied in linking claims, discloses the claimed invention but fail to disclose wherein the first and second switches are thyristors, such that the second terminal of the first switch and the first terminal of the second switch are cathodes of the respective switches that are coupled to the first node.
Chattopadhyay, in the same field of endeavor discloses, wherein the use of thyristors (for example see Fig. 18.1) that perform switching at a frequency of 10 kilohertz (kHz) as alternative for the transistors in a AC-AC converter (for example a AC Chopper).
Therefore, It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have optionally provide a first and a second switches as thyristors in Kusumoto view of He, as taught by Chattopadhyay, as a substitution for transistors in a AC- AC converter.
Allowable Subject Matter
Claims 6, 7, 9 and 12-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 6, the Prior art of record, as applied above, alone or in combination fail to disclose the first and second inductors have an inductance of an inductance of 2.5 millihenries (mH), and the first and second capacitors have a capacitance of 1 microFarad (uF).
Regarding claim 7, the Prior art of record, as applied above, alone or in combination fail to disclose the first and second inductors are transmission lines and the first and second capacitors are protective capacitors.
Regarding claim 9, the Prior art of record, as applied above, alone or in combination fail to disclose a first signal generator that provides a first square wave to the first switch based on the duty cycle; a second signal generator that provides a second square wave representing the total duty cycle length to a combinator; and a combinator signal generated by the combinator that is complimentary to the first square wave and is provided to the second switch.
Regarding claim 12, the Prior art of record, as applied above, alone or in combination fail to disclose wherein the first and second inductors have an inductance of an inductance of 2.5 millihenries (mH), the first and second capacitor have a capacitance of 1 microFarad (uF), and the first switch and second switch perform switching at a frequency of 10 kilohertz (kHz), such that the first switch and second switch have a total duty cycle length of 100 microseconds.
Claims 13-15 are dependent of claim 12.
Conclusion
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/YAHVEH COMAS TORRES/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838