DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to application filed on May 22, 2024.
Claims 1-20 are pending.
Claim Objections
Claims 1-20 are objected to because of the following informalities:
Claims 1, 11, 13 and 15-17 contain acronyms PLC, AP, MIL, SIL, HIL, and SMT throughout. It is recommended at the first instance of every acronym that they be spelled out such as “Programmable Logic Controller (PLC)”.
Claims 1, 5, 12, 14, 15 and 17-20 contain a “wherein” clause that further limits a claim limitation that has not yet been introduced. For example, in claim 1, it states “wherein a verified PLC algorithm…”. “[A] verified PLC algorithm” has not been introduced in claim 1, therefore, a “wherein” clause is not appropriate.
Claim 2 states “the function block”. In the interest of consistency, it is recommended that this limitation be amended to “the discrete-time deterministic function block”.
Claim 4 state “the modelled state” in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 5 states “both function blocks are the equal” and “both function blocks react…” in line 3. In the interest of consistency and to fix the grammatical error, it is recommended that this limitation be amended to “the function block and the deterministic function block are equal” and “the function block and the deterministic function block react…”.
Claims 7-9 state “the formal function block diagram algorithm…”. In the interest of consistency, it is recommended that this limitation be amended to “the functionally-equivalent formalized functional block diagram algorithm”.
Claims 9 and 12 states “the original functional block diagram algorithm” in lines 4 and 1 respectively. In the interest of consistency, it is recommended that this limitation be amended to “the functional block diagram algorithm”.
Claim 10 states “each deterministic function block”. In the interest of consistency, it is recommended that this limitation be amended to “each discrete-time deterministic function block”.
Claim 11 contains 2 sentences. A claim can only contain a single sentence.
Claim 15 states “separable component”, “the selected testing architecture” and “the resulting test scenarios” in line 13, 14 and 15 respectively. There is insufficient antecedent basis for this limitation in the claim. It is recommended that these limitations be amended to “a separable component”, “a selected testing architecture” and “the test scenarios”.
Claim 16 states “wherein exhausting generation of subcomponents’…” in line 1. In the interest of consistency, it is recommended that this limitation be amended to “wherein exhaustive generation of the subcomponents’ …”.
Claim 20 states “the combination operator” and “the grammar” in lines 3 and 4. There is insufficient antecedent basis for this limitation in the claim. It is recommended that these limitations be amended to “a combination operator” and “a grammar”.
Claims 2-14 and 16-20 depend on the objected to claims and do not resolve the deficiencies and thus, are objected to for at least the same reasons.
Appropriate correction is required.
Examiner would like request the applicant review all the claims to help identify any further issues that were not explicitly identified above.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 15 state “a functional block diagram algorithm” twice in lines 2 and 3 of claim 1 and lines 4 and 5 of claim 15. It is unclear if these are the same functional block diagram algorithm or different functional block diagram algorithms. In the interest of compact prosecution, the Examiner has interpreted them as being the same.
Claims 2 and 15 recite the limitation “the deterministic function block” in line 1. and 2 respectively There is insufficient antecedent basis for this limitation in the claim. It is unclear if the “wherein” clause is referring to the “discrete-time deterministic function blocks” (plural) or a “discrete-time deterministic function block” (singular).
Claim 2 states “a discrete time step k” twice in lines 8 and 18. It is unclear if these are the same discrete time or different discrete time. In the interest of compact prosecution, the Examiner has interpreted them as being the same.
Claims 2-4 and 15-18 uses the terms “block’s”, “model’s”, “algorithm’s”, “subcomponent’s”, “subcomponents’”, “blocks’” which denotes possession. It is unclear how the claim limitations following these terms are “possessed” by the terms. It is recommended that, for example, in claim 2 line 8, the claim limitation including the term be amended to “…represent values of the inputs of the function block”.
Claim 3 contain limitations in parenthesis “(model)”. It is unclear whether these claim limitations are part of the claimed invention. See MPEP § 2173.05(d).
Claims 4 and 11-13 contains limitations “its”. It is unclear what “its” is referring back to. It is recommended that “its” be replaced with the appropriate claim limitation that is being referred.
Regarding claim 9, the phrase "(i.e. replacing of all original function blocks of an original function block diagram by their functionally equivalent formal counterparts)" renders the claim indefinite because it is unclear whether the limitations following the phrase are part of the claimed invention. See MPEP § 2173.05(d).
Claim 14 states “at least one formal requirement” in lines 2-3. Claim 14 is dependent on claim 12 which already introduced “at least one formal requirement”. It is unclear if these are the same or different.
Claim 15 states “separable components” twice in lines 8 and 9. It is unclear if these are the same separable components or different separable components. In the interest of compact prosecution, the Examiner has interpreted them as being the same.
Claim 15 states “subcomponents’ pseudo test cases” twice in lines 10 and 12. It is unclear if these are the same subcomponents’ pseudo test cases or different subcomponents’ pseudo test cases. In the interest of compact prosecution, the Examiner has interpreted them as being the same.
Claim 15 states “joining them into test scenario” in lines 14. It is unclear what “them” is referring to.
The term “exhaustive” in claims 15 and 16 is a relative term which renders the claim indefinite. The term “exhaustive” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. It is unclear to what extent the “generation of subcomponents’ pseudo test cases from function blocks’ unit tests” is performed.
Claim 19 contains the term “some”. It is unclear what “some” is referring to. It is recommended that “some” be replaced with “a”.
Claims 2-14 and 16-20 depend on the rejected claims and do not resolve the deficiencies and thus, are rejected for at least the same reasons.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention recites a judicial exception, is directed to that judicial exception, an abstract idea, as it has not been integrated into practical application and the claims further do not recite significantly more than the judicial exception. Examiner has evaluated the claims under the framework provided in the 2019 Patent Eligibility Guidance published in the Federal Register 01/07/2019 and has provided such analysis below.
Step 1: Claims 1-20 are directed to methods and fall within the statutory category of processes. Therefore, “Are the claims to a process, machine, manufacture or composition of matter?” Yes.
In order to evaluate the Step 2A inquiry “Is the claim directed to a law of nature, a natural phenomenon or an abstract idea?” we must determine, at Step 2A Prong 1, whether the claim recites a law of nature, a natural phenomenon or an abstract idea and further whether the claim recites additional elements that integrate the judicial exception into a practical application.
Step 2A Prong 1:
Claim 1: The limitation “converting the functional block diagram algorithm into a functionally-equivalent formalized functional block diagram algorithm”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think and observe, judge and evaluate a functional block diagram algorithm and mentally convert, with or without the use of pen and paper, the functional block diagram algorithm into a functionally-equivalent formalized functional block diagram algorithm. The limitation “model checking the functionally-equivalent formalized functional block diagram algorithm”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think and observe, judge and evaluate a functionally-equivalent formalized functional block diagram algorithm and mentally model check, with or without the use of pen and paper, the functionally-equivalent formalized functional block diagram algorithm.
Claim 15: The limitation “parsing the functional block diagram algorithm into separable components”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think and observe, judge and evaluate a functional block diagram algorithm and mentally parse, with or without the use of pen and paper, the functional block diagram algorithm into separable components. The limitation “parsing separable components into tree-graph subcomponents”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think and observe, judge and evaluate separable components and mentally parse, with or without the use of pen and paper, the separable components into tree-graph subcomponents.
The limitation “exhaustive generation of subcomponents’ pseudo test cases from function blocks’ unit tests”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think and observe, judge and evaluate function blocks unit tests and mentally generate, with or without the use of pen and paper, subcomponents pseudo test cases from function blocks unit tests. The limitation “SMT based generation of test cases from subcomponents’ pseudo test cases”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think and observe, judge and evaluate subcomponents pseudo test cases and mentally generate, with or without the use of pen and paper, test cases from the subcomponents pseudo test cases based on SMT.
The limitation “modifying the test cases of separable component for the selected testing architecture and joining them into test scenarios”, as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think and observe, judge and evaluate tests cases of a separable component and mentally modify, with or without the use of pen and paper, the test cases of the separable component for a selected testing architecture and joining them into test scenarios.
Therefore, Yes, claims 1 and 15 recite judicial exceptions.
The claims have been identified to recite judicial exceptions, Step 2A Prong 2 will evaluate whether the claims are directed to the judicial exception.
Step 2A Prong 2:
Claim 1: The judicial exception is not integrated into a practical application. In particular, the claim recites the following additional elements - “obtaining a functional block diagram algorithm of a PLC” which is merely a recitation of insignificant data gathering activity (see MPEP § 2106.05(g)) which does not integrate a judicial exception into practical application and will also be addressed below in Step 2B as also being Well-Understood, Routine and Conventional. Further, claim 1 recites the following additional element - “wherein a verified PLC algorithm is a functional block diagram algorithm consisting of discrete-time deterministic function blocks with inputs, outputs and inner states which are downloaded into a target PLC and periodically executed” which is merely a recitation of field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate a judicial exception into a practical application.
Claim 15: The judicial exception is not integrated into a practical application. In particular, the claim recites the following additional elements – “using the resulting test scenarios and test cases for model-based grey-box testing in MIL, SIL and HIL testing of the PLC implementing these PLC algorithms” which is merely a recitation of generic computing components and functions being used as a tool to apply the abstract idea (see MPEP § 2106.05(f)) which does not integrate a judicial exception into practical application. Further, claim 15 recites the following additional elements - “obtaining a functional block diagram algorithm of a PLC” which is merely a recitation of insignificant data gathering activity (see MPEP § 2106.05(g)) which does not integrate a judicial exception into practical application and will also be addressed below in Step 2B as also being Well-Understood, Routine and Conventional. Further still, claim 15 recites the following additional element - “wherein a verified PLC algorithm is a functional block diagram algorithm consisting of discrete-time deterministic function blocks with inputs, outputs and inner states which are downloaded into a target PLC and periodically executed” which is merely a recitation of field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate a judicial exception into a practical application.
Therefore, “Do the claims recite additional elements that integrate the judicial exception into a practical application? No, these additional elements do not integrate the abstract idea into a practical application and they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
After having evaluating the inquires set forth in Steps 2A Prong 1 and 2, it has been concluded that claims 1 and 15 not only recite a judicial exception but that the claims are directed to the judicial exception as the judicial exception has not been integrated into a practical application.
Step 2B:
Claims 1 and 15: The claims do not include additional elements, alone or in combination, that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements amount to no more than generic computing components, mere instructions to apply an exception and/or field of use/technological environment which do not amount to significantly more than the abstract idea. Moreover, the recitations of insignificant data gathering activity as also Well-Understood, Routine and Conventional. See at least MPEP § 2106.05(d)(II) “The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. i. Receiving or transmitting data over a network, e.g., using the Internet to gather data”. That is, in the instant claims these limitations merely receive or transmit/provide data which is Well-Understood, Routine and Conventional.
Therefore, “Do the claims recite additional elements that amount to significantly more than the judicial exception? No, these additional elements, alone or in combination, do not amount to significantly more than the judicial exception.
Having concluded analysis within the provided framework, Claims 1 and 15 do not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 2, it recites additional element of “wherein the deterministic function block comprises a sextuple F(u, y, x, x0, f, g) such that: F: x(k + 1) = f (x(k), u(k)), k ∈ N0y(k) = g(x(k), u(k)),x(0) = x0,where u represents inputs, y represents outputs and x represents inner states of the function block, wherein u(k) ∈ FU , y(k) ∈ FY , x(k) ∈ FX represent values of the function block’s inputs, outputs and inner states at a discrete time step k, and x0∈ FX represents an initial value of the function block’s inner states; and wherein functions f() and g() comprise time-invariant deterministic functions defined as: f : (FU × FX) → FX, and g : (FU × FX) → FY; the function block’s inner states x are virtually divided into two groups: x = (xM, xA), x0 = (x0,M , x0,A), wherein xM represents modelled states and xA represents auxiliary states, xM(k) ∈FXMand xA(k) ∈FXA represent values of the function block’s modelled states and auxiliary states at a discrete time step k, and x0,M∈FXM, x0,A∈FXArepresent initial values of the function block’s modelled states and auxiliary states” which is merely a recitation of field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate a judicial exception into a practical application and does not amount to significantly more than the judicial exception. Further, claim 2 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 2 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 2 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 3, it recites additional element of “wherein the functional block diagram algorithm is defined by a quadruple M (F, u, y, R) where F is a finite set of function blocks, u represents (model) inputs, y represents (model) outputs, R is a finite set of oriented relations between function blocks, model inputs and model outputs, and u(k) ∈MU , y(k) ∈MY represent values of the model’s inputs and outputs at a discrete time step k ∈ N0” which is merely a recitation of field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate a judicial exception into a practical application and does not amount to significantly more than the judicial exception. Further, claim 3 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 3 also fails both Step 2A prong 3, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 3 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 4, it recites additional element of “wherein the modelled state comprises modelled states Fi.xM of the functional block diagram algorithm’s name-ordered function blocks Fi∈F, wherein the auxiliary state comprises auxiliary states Fi.xA of its name-ordered function blocks Fi∈F, wherein the relational state comprises inputs Fi.u and outputs Fi.y of its name-ordered function blocks Fi∈F, and wherein the complete state comprises the modelled state M.xM, the auxiliary state M.xA, the relational states M.r, the inputs M.u,and the outputs M.y” which is merely a recitation of field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate a judicial exception into a practical application and does not amount to significantly more than the judicial exception. Further, claim 4 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 4 also fails both Step 2A prong 3, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 4 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 5, it recites additional element of “wherein a function block is equivalent to the deterministic function block when inputs u, outputs y, modelled states xM and initial values of modelled states x0,M of both function blocks are the equal, and both function blocks react with equal current values of outputs y(k) and equal following values of modelled states xM(k + 1) for equal current values of inputs u(k) and modelled states xM(k) at any discrete time step k ∈ N0” which is merely a recitation of field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate a judicial exception into a practical application and does not amount to significantly more than the judicial exception. Further, claim 5 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 5 also fails both Step 2A prong 3, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 5 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 6, it recites additional abstract idea recitations of “wherein converting the functional block diagram algorithm into a functionally-equivalent functional block diagram algorithm comprises replacing each function block with the corresponding functionally-equivalent function block” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate a functional block diagram algorithm, just as in the independent claims above, mentally convert, with or without the use of pen and paper, the functional block diagram algorithm into a functionally-equivalent functional block diagram algorithm by replacing each function block with a corresponding functionally-equivalent function block. Further, claim 6 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 6 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 6 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 7, it recites additional element of “wherein the formal function block diagram algorithm comprises a finite-state model inscribed in a formal modelling language” which is merely a recitation of field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate a judicial exception into a practical application and does not amount to significantly more than the judicial exception. Further, claim 7 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 7 also fails both Step 2A prong 3, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 7 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 8, it recites additional element of “wherein the formal function block diagram algorithm comprises formal function blocks, each comprising a finite-state function block FF,i inscribed in a formal modelling language” which is merely a recitation of field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate a judicial exception into a practical application and does not amount to significantly more than the judicial exception. Further, claim 8 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 8 also fails both Step 2A prong 3, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 8 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 9, it recites additional element of “wherein the formal functional block diagram algorithm obtained by functionally-equivalent formalization (i.e. replacing of all original function blocks of an original function block diagram by their functionally-equivalent formal counterparts) is functionally-equivalent to the original functional block diagram algorithm” which is merely an insignificant data gathering activity (see MPEP § 2106.05(g)) which does not integrate a judicial exception into practical application and is also Well-Understood, Routine and Conventional. See at least MPEP § 2106.05(d)(II) “The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. i. Receiving or transmitting data over a network, e.g., using the Internet to gather data”. That is, in the instant claims these limitations merely receive or transmit/provide data which is Well-Understood, Routine and Conventional. Further, claim 8 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 9 also fails both Step 2A prong 3, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 9 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 10, it recites additional abstract idea recitations of “further comprising defining a formalized functionally-equivalent functional block for each deterministic function block” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate each deterministic function block, just as in the independent claims above, mentally define, with or without the use of pen and paper, a formalized functionally-equivalent functional block for each deterministic function block. Further, claim 10 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 10 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 10 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 11, it recites additional abstract idea recitations of “proving that any formal finite-state function block diagram can be represented by a Kripke structure with AP consisting of all its variables” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate any formal finite-state function block diagram, just as in the independent claims above, mentally prove, with or without the use of pen and paper, that any formal finite-state function block diagram can be represented by a Kripke structure with AP consisting of all its variables. Further, claim 11 recites additional abstract idea recitations of “Hence, any formal finite-state function block diagram can be verified by model checking against formal requirements constructed from atomic requirements AP consisting of all its variables” s drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate any formal finite-state function block diagram, just as in the independent claims above, mentally verify, with or without the use of pen and paper, any formal finite-state function block diagram by model checking against formal requirements constructed from atomic requirements AP consisting of all its variables. Further still, claim 11 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 11 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 11 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 12, it recites additional abstract idea recitations of “wherein checking the original functional block diagram algorithm comprises checking its functionally-equivalent formalized functional block diagram algorithm against at least one formal requirement” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate functionally-equivalent formalized functional block diagram algorithm, just as in the independent claims above, mentally check, with or without the use of pen and paper, the functionally-equivalent formalized functional block diagram algorithm against at least one formal requirement. Further, claim 12 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 12 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 12 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 13, it recites additional abstract idea recitations of “further comprising defining the at least one formal requirement on subset of atomic requirements AP consisting of its all-modelled variables” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate atomic requirements AP, just as in the independent claims above, mentally define, with or without the use of pen and paper, at least one formal requirement on the subset of atomic requirements AP consisting of its all-modelled variables. Further, claim 13 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 13 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 13 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 14, it recites additional abstract idea recitations of “wherein results for checking the formalized functionally-equivalent functional block diagram algorithm against at least one formal requirement are assumed to be valid for the original functional block diagram algorithm” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate results, just as in the independent claims above, mentally assume, with or without the use of pen and paper, the results for checking the formalized functionally-equivalent functional block diagram algorithm against at least one formal requirement are valid for the original functional block diagram algorithm. Further, claim 14 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 14 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 14 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 16, it recites additional abstract idea recitations of “wherein exhausting generation of subcomponents’ pseudo test cases from function blocks’ unit tests and SMT based generation of test cases from subcomponents’ pseudo test cases comprises resolving of assume-guarantee value requirements from a model’s function blocks’ unit tests by traversing all requested value requirements to model inputs and all proving value requirements to model outputs” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate a model function block unit tests, just as in the independent claims above, mentally resolve, with or without the use of pen and paper, assume-guarantee value requirements from the model function blocks unit tests by traversing all requested value requirements to model inputs and all proving value requirements to model outputs. Further, claim 16 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 16 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 16 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 17, it recites additional abstract idea recitations of “wherein SMT based generation of test cases from subcomponents’ pseudo test cases comprises generating, by a combination of compatible subcomponents’ pseudo test cases PTCSCJτ shifted in time τ” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate test cases from subcomponent pseudo test cases, just as in the independent claims above, mentally generate, with or without the use of pen and paper, the test cases from subcomponents pseudo test cases by using a combination of compatible subcomponent’ pseudo test cases PTCSCJτ shifted in time τ. Further, claim 17 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 17 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 17 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 18, it recites additional abstract idea recitations of “wherein an algorithm generates a complete set of pseudo test cases PTCSCJ for a subcomponent SCJ by combining the subcomponent’s function blocks’ unit tests UTFi shifted in time τ” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can think about and observe, judge and evaluate a complete set of pseudo test cases, just as in the independent claims above, mentally generate, with or without the use of pen and paper, the complete set of pseudo test cases PTCSCJ for a subcomponent SCJ by combining the subcomponent’s function blocks’ unit tests UTFi shifted in time τ. Further, claim 18 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 18 also fails both Step 2A prong 2, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 18 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 19, it recites additional element of “wherein a specified assume-guarantee value requirement (v, k, c) requires some variable v at some discrete time step k to have some specific constant value c” which is merely a recitation of field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate a judicial exception into a practical application and does not amount to significantly more than the judicial exception. Further, claim 19 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 19 also fails both Step 2A prong 3, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 19 does not recite patent eligible subject matter under 35 U.S.C. § 101.
With regard to claim 20, it recites additional element of “wherein a combination of required values r1, r2 of two assume-guarantee value requirements rv1(v, k, r1), rv2(v, k, r2) can be denoted as r1∧ r2, where the combination operator is commutative and associative, wherein the combination of the required values follows the grammar of assume-guarantee value requirements” which is merely a recitation of field of use/technological environment (see MPEP § 2106.05(h)) which does not integrate a judicial exception into a practical application and does not amount to significantly more than the judicial exception. Further, claim 20 does not recite any further additional elements and for the same reasons as above with regard to integration into practical application and whether additional elements amount to significantly more, claim 20 also fails both Step 2A prong 3, thus the claim is directed to the judicial exception as it has not been integrated into practical application, and fails Step 2B as not amounting to significantly more. Therefore, claim 20 does not recite patent eligible subject matter under 35 U.S.C. § 101.
Therefore, Claims 1-20 do not recite patent eligible subject matter under 35 U.S.C. §101.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 6-10 and 12-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tomas Ausberger et al. (“Analytic method for automatic test case generation for Function Block Diagram”, Oct 2020).
With respect to Claim 1, Tomas Ausberger et al. disclose:
obtaining a functional block diagram algorithm of a PLC, (see Figure 1; an original model (functional block diagram algorithm) is developed, 1. Introduction, Paragraphs 1 and 2; FBD is a graphical language for programmable logic controllers (PLC), II. Assumptions, Paragraph 1) wherein a verified PLC algorithm (the original model can be verified by formal verification methods (e.g. Model Checking), 1. Introduction, Paragraph 2, lines 1-3) is a functional block diagram algorithm consisting of discrete-time deterministic function blocks with inputs, outputs and inner states which are downloaded into a target PLC (All models are considered in a form of FBD. The FBD model can be interpreted as a directed graph, where nodes are the blocks, and edges represent the signals between the blocks. In the following sections the graph will be considered as a directed acyclic graph. Thus, the considered FBD model will not contain any feedback loop.
The function of a block can be described by following equations.
xi,k+1 = fi(xi,k,ui,k); ∀k ∈ N0
yi,k = gi(xi,k,ui,k)
xi,0 ∈ I0
x, y and u are the vectors of the block inner states, its outputs and inputs. The first subscript i denotes a name of the block and the second k denotes a discrete time step. The value of the state is determined by the function fi and the output value is determined by the function gi. Both functions are functions of the inner states and block inputs. I0 represents a set of vectors with initial states., II. Assumptions, C. Model assumptions, Paragraphs 1 and 2; A FBD model can be designed in REXYGEN STUDIO, compiled by RexComp and downloaded to target RexCore, III. Process, B. Used tools, Paragraph 1) and periodically executed; (The original model has to be implemented by a discrete control system with a fixed execution period. After the initialization this system periodically updates all blocks with current values of system inputs., II. Assumptions, C. Model assumptions, Paragraph 4)
converting the functional block diagram algorithm into a functionally-equivalent formalized functional block diagram algorithm; (see Figure 1; the model has to be formalized, I. Introduction, Paragraph 2, lines 4-5; formalizing function blocks that consists of blocks with real-time function using a proper conversion from real time to discrete time, II. Assumptions, Paragraph 3)
and model checking the functionally-equivalent formalized functional block diagram algorithm. (see Figure 1; This can be achieved by additional Model In the Loop (MIL) testing of the original (or formal) model, I. Introduction, Paragraph 2, lines 10-11)
With respect to Claim 6, all the limitations of Claim 1 have been addressed above; and Tomas Ausberger et al. further disclose:
wherein converting the functional block diagram algorithm into a functionally-equivalent functional block diagram algorithm comprises replacing each function block with the corresponding functionally-equivalent function block. (formalizing function blocks (converting) that consists of blocks with real-time function using a proper conversion (replacing) from real time to discrete time (corresponding functionally-equivalent), II. Assumptions, Paragraph 3)
With respect to Claim 7, all the limitations of Claim 1 have been addressed above; and Tomas Ausberger et al. further disclose:
wherein the formal function block diagram algorithm comprises a finite-state model inscribed in a formal modelling language. (The presented approach is based on discrete time and finite state automata, I. Introduction, Paragraph 6; Model Checking is a method of formal verification which can be used to prove the formal model complies with the original requirements. These requirements have to be specified in a formal language. Model Checking verifies whether the formal model does not violate the specified requirements in any state or sequence of states., I. Introduction, Paragraph 3)
With respect to Claim 8, all the limitations of Claim 1 have been addressed above; and Tomas Ausberger et al. further disclose:
wherein the formal function block diagram algorithm comprises formal function blocks, each comprising a finite-state function block FF,i inscribed in a formal modelling language. (The presented approach is based on discrete time and finite state automata, I. Introduction, Paragraph 6; Model Checking is a method of formal verification which can be used to prove the formal model complies with the original requirements. These requirements have to be specified in a formal language. Model Checking verifies whether the formal model does not violate the specified requirements in any state or sequence of states. (finite-state function block), I. Introduction, Paragraph 3)
With respect to Claim 9, all the limitations of Claim 1 have been addressed above; and Tomas Ausberger et al. further disclose:
wherein the formal functional block diagram algorithm obtained by functionally-equivalent formalization (i.e. replacing of all original function blocks of an original function block diagram by their functionally-equivalent formal counterparts) is functionally-equivalent to the original functional block diagram algorithm. (see Figure 1; the model has to be formalized, I. Introduction, Paragraph 2, lines 4-5; formalizing function blocks that consists of blocks with real-time function using a proper conversion from real time to discrete time (functionally-equivalent to the original functional block diagram algorithm), II. Assumptions, Paragraph 3)
With respect to Claim 10, all the limitations of Claim 1 have been addressed above; and Tomas Ausberger et al. further disclose:
further comprising defining a formalized functionally-equivalent functional block for each deterministic function block. (converting the original model (function block) into a formal model (functionally-equivalent functional block) wherein the original model is in the form of FBD wherein the block is deterministic, II. Assumptions, C. Model assumptions, Paragraph 2)
With respect to Claim 12, all the limitations of Claim 1 have been addressed above; and Tomas Ausberger et al. further disclose:
wherein checking the original functional block diagram algorithm comprises checking its functionally-equivalent formalized functional block diagram algorithm against at least one formal requirement. (Model Checking is a method of formal verification which can be used to prove the formal model complies with the original requirements. These requirements have to be specified in a formal language. Model Checking verifies whether the formal model (functionally-equivalent formalized functional block diagram algorithm) does not violate the specified requirements ( at least one formal requirement) in any state or sequence of states., 1. Introduction, Paragraph 3)
With respect to Claim 13, all the limitations of Claim 12 have been addressed above; and Tomas Ausberger et al. further disclose:
further comprising defining the at least one formal requirement on subset of atomic requirements AP consisting of its all-modelled variables. (original requirements can be specified in a formal language (formal requirement) and define specific conditions, states or sequence of states (subset of atomic requirements AP/all-modelled variables), I. Introduction, Paragraph 3)
With respect to Claim 14, all the limitations of Claim 12 have been addressed above; and Tomas Ausberger et al. further disclose:
wherein results for checking the formalized functionally-equivalent functional block diagram algorithm against at least one formal requirement are assumed to be valid for the original functional block diagram algorithm. (If the tests prove (results) with
high level of certainty that the behaviour of the implemented system is the same as the behaviour of the model (original functional block diagram algorithm) then the results of the model formal verification can be anticipated for the implemented system (assume valid)., I. Introduction, Paragraph 2, lines 16-20)
With respect to Claim 15, Tomas Ausberger et al. disclose:
obtaining a functional block diagram algorithm of a PLC, (an original model (functional block diagram algorithm) is developed, 1. Introduction, Paragraphs 1 and 2; FBD is a graphical language for programmable logic controllers (PLC), II. Assumptions, Paragraph 1 wherein a verified PLC algorithm (the original model can be verified by formal verification methods (e.g. Model Checking), 1. Introduction, Paragraph 2, lines 1-3) is a functional block diagram algorithm consisting of discrete-time deterministic function blocks with inputs, outputs and inner states which are downloaded into a target PLC (All models are considered in a form of FBD. The FBD model can be interpreted as a directed graph, where nodes are the blocks, and edges represent the signals between the blocks. In the following sections the graph will be considered as a directed acyclic graph. Thus, the considered FBD model will not contain any feedback loop.
The function of a block can be described by following equations.
xi,k+1 = fi(xi,k,ui,k); ∀k ∈ N0
yi,k = gi(xi,k,ui,k)
xi,0 ∈ I0
x, y and u are the vectors of the block inner states, its outputs and inputs. The first subscript i denotes a name of the block and the second k denotes a discrete time step. The value of the state is determined by the function fi and the output value is determined by the function gi. Both functions are functions of the inner states and block inputs. I0 represents a set of vectors with initial states., II. Assumptions, C. Model assumptions, Paragraphs 1 and 2; A FBD model can be designed in REXYGEN STUDIO, compiled by RexComp and downloaded to target RexCore, III. Process, B. Used tools, Paragraph 1) and periodically executed; (The original model has to be implemented by a discrete control system with a fixed execution period. After the initialization this system periodically updates all blocks with current values of system inputs., II. Assumptions, C. Model assumptions, Paragraph 4)
parsing the functional block diagram algorithm into separable components; (The model (functional block diagram) is first checked and divided into separated components, IV. The Principles of Test Generation, A. Separated components, Paragraph 1)
parsing separable components into tree-graph subcomponents; (see Figure 4; the separated components consists of a set of not fully tested blocks (subcomponents) and an initial block is chosen and blocks without any successors (tree-graph representation/structure) are preferred, V. Algorithm, Paragraph 4; generate an oriented graph (tree-graph) where nodes represent chosen unit tests of each block at a discrete time step and edges represent signals between the blocks, IV. The Principles of Test Generation, D. Path searching, Paragraph 2)
exhaustive generation of subcomponents’ pseudo test cases from function blocks’ unit tests; (see Figure 4; test case generation is repeated until all separated components are fully tested by the generated test set (exhaustive generation), V. The Algorithm, Paragraph 1; If the block is unresolved, a compatible unit test is searched (generation of subcomponents pseudo test cases from function blocks unit tests, V. Algorithm, Paragraph 5)
SMT based generation of test cases from subcomponents’ pseudo test cases; (see Figure 4; the selected unit test is stored and the inputs of the currently processed block are processed. The inputs are checked and processed from the first to the last. First, the check is performed if the predecessor of the block connected to the selected input is an unresolved junction at any time step (step 6). If there is no unresolved junction, an unresolved block is searched on the input (step 8). If there is an unresolved block, this block is selected as currently processed (step 9) and a compatible unit test is searched (step 4). If there is no unresolved block on the block input, an unresolved block on the block output is searched (step 10). If there is such a block, it is selected and processed (steps 9 and 4). If there is no unresolved block on the block output, the status of other blocks in the separated component is checked (step 11). If there is still any unresolved block, the algorithm returns back to the last processed block (step 12), and continues in searched in the unresolved block on the inputs and outputs. If all blocks in the model are resolved, the test generation is completed, V. Algorithm, Paragraph 6)
modifying the test cases of separable component for the selected testing architecture and joining them into test scenarios; (The final test case is produced by expressing (modifying) the values of system inputs and outputs from the selected unit tests at each time step. The test case generation is repeated until all blocks (test cases) are fully tested (test scenario), V. Algorithm, Paragraph 8)
and using the resulting test scenarios and test cases for model-based grey-box testing in MIL, SIL and HIL testing of the PLC implementing these PLC algorithms. (The generated test cases are used for SIL and HIL testing of the implemented system. The generated test cases should be also verified which can be achieved by additional Model In the Loop (MIL) testing of the original (or formal) model, 1. Introduction, Paragraph 2, lines 2-16; The test cases are designed to be used for gray-box testing of the implemented model, Abstract, lines 7-10)
Allowable Subject Matter
Claims 2-5, 11 and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and any objections, 112 and 101 rejections are overcome.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Reynolds et al. (US 2023/0297060) discloses machine learning optimization of control code in an industrial automation environment.
Okazaki et al. (US 2019/0391910) discloses a software testing device that includes a conversion unit for converting a PLC program into a general purpose language program and test execution unit to perform a test on the general purpose language program.
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