DETAILED ACTION
This action is responsive to the following: The request for continued examination filed on July 28, 2026 and the amendments to claims and arguments made in amendment filed on July 13, 2026.
Claims 1-20 are pending. Claims 1, 10, and 19 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 13, 2026 has been entered.
Response to Amendment
The amendments to claims and specification filed on July 13, 2026 are entered. Claims 1-20 remain pending.
Specification: Application Title
Applicant submitted a more descriptive title on January 2, 2026. The new title shall be: “METHODS AND APPARATUSES FOR MANAGING OVER-PROGRAMMING IN MEMORY DEVICES”. The new title has been recorded on applicant’s Bibliography Data Sheet. No further action is required by the applicant. The examiner will change the name as part of the Examiner’s Amendment process if an allowance is processed.
Filing Date 3/11/2024 - Benefit Claim Perfected
Instant application is a bypass-continuation of international application PCT/CN2024/080907 filed March 11, 2024, which designated the US and published in English as WO 2025/189309 A1. The disclosures have been compared and they are identical (except for instant application’s first paragraph, which indicates the benefit claim to PCT/CN2024/080907). Therefore, instant application is entitled to the filing date of March 11, 2024. MPEP 1895.01.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 6-8, 10-12, 14-16, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Parker (US 20130322181 A1).
Regarding Independent Claim 1, Parker teaches a method of operating a memory device, comprising:
receiving an erase command indicating to erase a memory block of the memory device (para 39 “Decoder 481 and decoder 482 can each receive address bus information from controller 436 and can utilize such information to facilitate accessing or selecting the desired memory cell(s) (e.g., memory location(s)) associated with the command, and to provide the needed voltages to the bit lines (decoder 481) and the word lines (decoder 482) according to timing that is controlled by controller 436.”; para 29 “Memory controller 330 is configured to control program operations and erase operations to memory cells 310.”);
before erasing the memory block (para 29 “When memory controller 330 performs erase operation to memory cells 310, the erase operation includes a programming phase that occurs prior to the actual erase.”):
programming memory cells in the memory block to a pre-programmed state (para 29 “This programming phase that occurs within the erase operation may be referred to as “pre-programming”.”); and
identifying a threshold voltage of the memory cells in the pre-programmed state (para 29 “During the pre-programming, some of the bits are being changed from the un-programmed state to the programmed state, and pulses are applied until a program verify is passed as discussed above. The number of pulses applied in that sector is stored.”); and
after erasing the memory block (para 29 “When memory controller 330 performs erase operation to memory cells 310, the erase operation includes a programming phase that occurs prior to the actual erase.”),
performing a program operation to programing memory cells (para 50 “ The stored number of pulses for that sector is used in later programming operations for that sector. “) in the memory block using at least one program pulse with a program voltage lower than a pre-defined program voltage (para 51 “If less that than the optimum number of pulses was needed until the program verify passed, then programming occurred too fast, so the program voltage is decreased.”) when the threshold voltage is higher than a pre-set voltage.
Regarding Claim 2, Parker teaches the limitations of Claim 1. Parker teaches wherein the threshold voltage of the memory cells in the pre-programmed state increases with an increase of a quantity of erase operations performed on the memory block (para 47 “as memory device 400 cycles and ages, without applying the adaptive adjustments, the read margin would degrade.”).
Regarding Claim 3, Parker teaches the limitations of Claim 1. wherein programing the memory cells in the memory block to the pre-programmed state comprises:
programming memory cells in an erased state to the pre-programmed state (para 49 “ During the pre-programming, some of the bits are being changed from the un-programmed state to the programmed state”.”).
Regarding Claim 6, Parker teaches the limitations of Claim 1. Parker teaches wherein the memory cells are single-level cells (para 35 “In a single-level cell ("SLC") device, each cell stores only one bit of information, either the cell is "un-programmed" (has a "1" value) or "programmed" (has a "0" value).”), wherein the at least one program pulse is a single program pulse, and wherein at least one of a program voltage of the single program pulse or a pulse length of the single program pulse is determined based on the threshold voltage (para 50 “This stored number is used to adjust subsequent programming operations to adjust the program voltage, if needed.”).
Regarding Claim 7, Parker teaches the limitations of Claim 6. Parker further teaches wherein the program voltage is lower than a pre-defined program voltage, wherein a difference between the pre-defined program voltage and the program voltage is positively correlated to a value of the threshold voltage (para 51 “The stored number of pulses required during the last pre-programming phase is used to adjust the program voltage used in subsequent program operations. If less than the optimum number of pulses was needed until the program verify passed, then programming occurred too fast, so the program voltage is decreased. If more than the optimum number of pulses was needed until the program verify passed, then programming occurred too slowly, so that the program voltage is increased. If exactly the optimum number of pulses is used, the program voltage remains unchanged. For example, a program voltage may be 9.5 V at BOL, may be gradually decreased over the age of the device to about 8.5 V, and increased again near the EOL of memory device 400. In each case, the changes are based on the stored number of pulses required for program verify during the pre-programming phase of the last erase operation. In some embodiments, the initial value used before the first erase operation is factory-tuned.”).
Regarding Claim 8, Parker teaches the limitations of Claim 1. Parker further teaches wherein the memory cells are multi-level cells (para 35 “There also exist multi-level cell (“MLC”) devices that can store more than one bit per cell by choosing between multiple levels of electrical charge to apply to the floating gates of its cells. “), wherein the at least one program pulse are a plurality of program pulses, and wherein at least one of a program voltage of a starting program pulse of the plurality of the program pulses or a pulse length of the plurality of program pulses is determined based on the threshold voltage (para 50 “This stored number is used to adjust subsequent programming operations to adjust the program voltage, if needed.”).
Regarding Independent Claim 10, Parker teaches memory device comprising:
a memory array (Fig. 1: 110) comprising memory blocks (Fig. 1: 120) ; and
a peripheral circuit (Fig. 1: 130) configured to perform operations comprising:
receiving an erase command indicating to erase a memory block of the memory device (para 39 “Decoder 481 and decoder 482 can each receive address bus information from controller 436 and can utilize such information to facilitate accessing or selecting the desired memory cell(s) (e.g., memory location(s)) associated with the command, and to provide the needed voltages to the bit lines (decoder 481) and the word lines (decoder 482) according to timing that is controlled by controller 436.”; para 29 “Memory controller 330 is configured to control program operations and erase operations to memory cells 310.”);
erasing a memory block (para 29 “When memory controller 330 performs erase operation to memory cells 310, the erase operation includes a programming phase that occurs prior to the actual erase.”):
performing a first program operation to programing memory cells in the memory block to a pre-programmed state (para 29 “This programming phase that occurs within the erase operation may be referred to as “pre-programming”.”); and
identifying a threshold voltage of the memory cells in the pre-programmed state (para 29 “During the pre-programming, some of the bits are being changed from the un-programmed state to the programmed state, and pulses are applied until a program verify is passed as discussed above. The number of pulses applied in that sector is stored.”); and
after erasing the memory block (para 29 “When memory controller 330 performs erase operation to memory cells 310, the erase operation includes a programming phase that occurs prior to the actual erase.”) performing a program operation to programing memory cells (para 50 “ The stored number of pulses for that sector is used in later programming operations for that sector. “) in the memory block using at least one program pulse with a program voltage lower than a pre-defined program voltage (para 51 “If less that than the optimum number of pulses was needed until the program verify passed, then programming occurred too fast, so the program voltage is decreased.”) when the threshold voltage is higher than a pre-set voltage.
Regarding Claim 11, Parker teaches the limitations of Claim 10.
Claim 12 is rejected for the same reasons as Claim 2.
Regarding Claim 12, Parker teaches the limitations of Claim 10.
Claim 12 is rejected for the same reasons as Claim 3.
Regarding Claim 14, Parker teaches the limitations of Claim 10.
Claim 14 is rejected for the same reasons as Claim 6.
Regarding Claim 15, Parker teaches the limitations of Claim 14.
Claim 15 is rejected for the same reasons as claim 7.
Regarding Claim 16, Parker teaches the limitations of Claim 10.
Claim 16 is rejected for the same reasons as Claim 8.
Regarding Claim 18, Parker teaches the limitations of Claim 10. Parker further teaches wherein the memory device comprises a NAND memory device (para 22 “In some embodiments, memory 100 is a flash-based memory including flash-based memory cells, such as flash-based NAND cells,”).
Regarding Independent Claim 19, Parker teaches a memory system comprising:
a memory controller (Fig. 1: 136); and
a memory device (Fig. 1: 110) coupled to the memory controller (Fig. 1: 136), wherein the memory device (Fig. 1: 110) is configured to perform operations comprising:
receiving an erase command indicating to erase a memory block of the memory device (para 39 “Decoder 481 and decoder 482 can each receive address bus information from controller 436 and can utilize such information to facilitate accessing or selecting the desired memory cell(s) (e.g., memory location(s)) associated with the command, and to provide the needed voltages to the bit lines (decoder 481) and the word lines (decoder 482) according to timing that is controlled by controller 436.”; para 29 “Memory controller 330 is configured to control program operations and erase operations to memory cells 310.”);
erasing a memory block (para 29 “When memory controller 330 performs erase operation to memory cells 310, the erase operation includes a programming phase that occurs prior to the actual erase.”):
programming memory cells in the memory block to a pre-programmed state (para 29 “This programming phase that occurs within the erase operation may be referred to as “pre-programming”.”); and
identifying a threshold voltage of the memory cells in the pre-programmed state (para 29 “During the pre-programming, some of the bits are being changed from the un-programmed state to the programmed state, and pulses are applied until a program verify is passed as discussed above. The number of pulses applied in that sector is stored.”); and
after erasing the data in the memory block (para 29 “When memory controller 330 performs erase operation to memory cells 310, the erase operation includes a programming phase that occurs prior to the actual erase.”)
performing a program operation to programing memory cells (para 50 “ The stored number of pulses for that sector is used in later programming operations for that sector. “) in the memory block using at least one program pulse with a program voltage lower than a pre-defined program voltage (para 51 “If less that than the optimum number of pulses was needed until the program verify passed, then programming occurred too fast, so the program voltage is decreased.”) when the threshold voltage is higher than a pre-set voltage.
Regarding Claim 20, Parker teaches the limitations of Claim 19.
Claim 20 is rejected for the same reasons as claim 7.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Parker et al (US 20130322181 A1) and Prakash et al (US 20250061948)
Regarding Claim 4, Parker teaches the limitations of Claim 1. Parker teaches identifying the threshold voltage (para 29 “During the pre-programming, some of the bits are being changed from the un-programmed state to the programmed state, and pulses are applied until a program verify is passed as discussed above. The number of pulses applied in that sector is stored.”)
Parker fails determining failed bit counts in order to identify the threshold voltage.
Prakash however teaches determining a set of fail bit counts (FBCs) of the memory cells corresponding to the set of the read voltages (Fig. 1C: 162);
and applying a set of read voltages to the memory cells (Fig. 16: VREAD_NS, VREADK_NS; Fig. 17: VREAD_PS, VREADK_PS)
Counting the number of failed bits is useful because it allows you to determine whether or not the program voltage needs to be adjusted using a simple binary of pass fail. From there if it is determined an adjustment needs to be made finer tuning can be done by sensing the threshold voltages to adjust the program voltage as desired in response to the threshold voltage sensed.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Prakash to the teachings of Parker to produce a method of adjusting the threshold voltage that involves determining a set of failed bit counts.
Regarding Claim 5, Parker and Prakash teaches the limitations of Claim 4. Prakash further teaches comparing the set of FBCs to a threshold (Fig. 1C: 162), wherein a FBC associated with a read voltage of the set of the read voltages that is identified as the threshold voltage is less than the threshold (Fig.1C: 163).
Regarding Claim 13, Parker teaches the limitations of Claim 10.
Claim 13 is rejected for the same reasons as Claim 4.
Claims 9 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Parker et al (US 20130322181 A1) and Guo et al (US 20230154550).
Regarding Claim 9, Parker teaches the limitations of Claim 1. Parker fails to teach wherein a quantity of erase operations performed on the memory block is greater than a pre-determined threshold.
Guo teaches performing and additional erase operation beyond a predetermined threshold (para 122 “If the result (N2−N1) is greater than or equal to the Threshold, then an extra erase operation”)
Guo states the rationale for this is “ to reduce the threshold voltages of the memory cells of the edge word lines to align more closely with the threshold voltages of the other data word lines.” Thus, there would be an advantage in monitoring the threshold voltages of the cells and when a certain threshold of a number of cycles has been reached performing a greater quantity of Erase cycles than the threshold in order to produce a more uniform threshold distribution across the cells in the array.
It would have therefore been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Guo to the teachings of Parker to produce a method of programming a memory where more erase cycles are performed than a pre-defined threshold.
Regarding Claim 17, Parker teaches the limitations of Claim 10.
Claim 17 is rejected for the same reasons as Claim 9.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH FIDELIS STORMES whose telephone number is (571)272-3443. The examiner can normally be reached M-F: 6:30am-4pm CST.
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/JOSEPH FIDELIS STORMES/Examiner, Art Unit 2825
/Donald HB Braswell/Primary Examiner, Art Unit 2825
