DETAILED ACTION
This action is responsive to the following: The amendment to claims and arguments filed in amendment filed on January 2, 2026.
Claims 1-20 are pending. Claims 1, 10, and 19 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Filing Date 3/11/2024 - Benefit Claim Perfected
Instant application is a bypass-continuation of international application PCT/CN2024/080907 filed March 11, 2024, which designated the US and published in English as WO 2025/189309 A1. The disclosures have been compared and they are identical (except for instant application’s first paragraph, which indicates the benefit claim to PCT/CN2024/080907). Therefore, instant application is entitled to the filing date of March 11, 2024. MPEP 1895.01.
Response to Amendment
The amendments to claims and specification filed on January 2, 2026 are entered. Claims 1-20 remain pending. The amendment to specification over comes the objection set forth in the previous non-final office action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 8, 10-12, 16, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Kamei et al (US 20080158980).
Regarding Independent Claim 1, Kamei teaches a method of operating a memory device, comprising:
erasing data in a memory block of the memory device (Fig. 16: 1202):
performing a first program operation to programing memory cells in the memory block to a pre-programmed state (Fig. 16: 1204); and
identifying a threshold voltage of the memory cells in the pre-programmed state (Fig. 16: 1206); and
after erasing the data in the memory block (Fig. 16: 1202),
performing a next program operation of the first program operation to programing memory cells (Fig. 16: 1210-1216) in the memory block using at least one program pulse (Fig. 16: 1208) with a program voltage (para 90: Vpgm(0)) lower (see para 90, explaining “Vpgm(0)=Vpgm_nomimal - 3(DAC)”) than a pre-defined program voltage (para 90 “Vpgm_nominal”) for the next program operation when the threshold voltage (para 90 “Vth_trial”) is higher than a pre-set voltage (para 90 “VtrH”).
Kamei fails to teach that the pre-program step and identification of threshold voltage step happen before the block is erased. However, applicant’s claims represent an obvious variant of Kamei’s. MPEP 2144.04(IV)(C) states “selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results.” It would be obvious variant to merely use a different program pulse adjusted to program cells from an erased state using threshold voltages measured after in a pre-program operation, rather than setting it based on programming from a pre-programmed state.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Kamei to produce the method of programming a memory consisting of a pre-programming step followed by a threshold voltage identification step, an erase step, and finally a programming step where the programming process uses the threshold voltages identified in preprogramming to program the cells.
Regarding Claim 2, Kamei teaches the limitations of Claim 1. Kamei teaches wherein the threshold voltage of the memory cells in the pre-programmed state increases with an increase of a quantity of erase operations performed on the memory block (Para 11; “However, as a non-volatile memory device undergoes many programming cycles, charge becomes trapped in the insulation between the floating gate and the channel region. This trapping of charge shifts the threshold voltage to a higher level” An erase operation is understood to be part of program cycle.).
Regarding Claim 3, Kamei teaches the limitations of Claim 1. wherein programing the memory cells in the memory block to the pre-programmed state comprises:
programming memory cells in an erased state (Fig. 16: 1202) 1to the pre-programmed state (Fig. 16: 1204).
Regarding Claim 8, Kamei teaches the limitations of Claim 1. Kamei further teaches wherein the memory cells are multi-level cells (para 39 “A memory cell can also store multiple levels of information (referred to as a multi-state memory cell), wherein the at least one program pulse are a plurality of program pulses, and wherein at least one of a program voltage of a starting program pulse of the plurality of the program pulses or a pulse length of the plurality of program pulses is determined based on the threshold voltage (Fig. 16: 1208).
Regarding Independent Claim 10, Kamei teaches memory device comprising:
a memory array (Fig. 4: 200) comprising memory blocks (Fig. 4: Block 0-1023); and
a peripheral circuit (Fig. 3: 220, 230A-B, 243A-B, 244) configured to perform operations comprising:
erasing data in a memory block (Fig. 16: 1202):
performing a first program operation to programing memory cells in the memory block to a pre-programmed state (Fig. 16: 1204); and
identifying a threshold voltage of the memory cells in the pre-programmed state (Fig. 16: 1206); and
after erasing data in the memory block (Fig. 16: 1202) performing a next program operation of the first program operation to program memory cells (Fig. 16: 1210-1216) in the memory block using at least one program pulse with a program voltage lower (para 90 “Vpgm(0)=Vpgm_nomimal-3(DAC)”) than a pre-defined program voltage (para 90 “Vpgm_nominal”) for the next program operation when the threshold voltage (para 90 “Vth_trial”) is higher than a pre-set voltage (para 90 “VtrH”).
Kamei fails to teach that the pre-program step and identification of threshold voltage step happen before the block is erased. However, applicant’s claims represent an obvious variant of Kamei’s. MPEP 2144.04(IV)(C) states “selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results.” It would be obvious variant to merely use a different program pulse adjusted to program cells from an erased state using threshold voltages measured after in a pre-program operation, rather than setting it based on programming from a pre-programmed state.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Kamei to produce the memory which is programmed using a method consisting of a pre-programming step followed by a threshold voltage identification step, an erase step, and finally a programming step where the programming process uses the threshold voltages identified in preprogramming to program the cells.
Regarding Claim 11, Kamei teaches the limitations of Claim 10.
Claim 12 is rejected for the same reasons as Claim 2.
Regarding Claim 12, Kamei teaches the limitations of Claim 10.
Claim 12 is rejected for the same reasons as Claim 3.
Regarding Claim 16, Kamei teaches the limitations of Claim 10.
Claim 16 is rejected for the same reasons as Claim 8.
Regarding Claim 18, Kamei teaches the limitations of Claim 10. Kamei further teaches wherein the memory device comprises a NAND memory device (Fig. 4: block I; para 35).
Regarding Independent Claim 19, Kamei teaches a memory system comprising:
a memory controller (Fig. 3: 244); and
a memory device (Fig. 3: 212) coupled to the memory controller (Fig. 3: 244), wherein the memory device (Fig. 3: 212) is configured to perform operations comprising:
erasing data in a memory block of the memory device (Fig. 16: 1202):
performing a first program operation to programing memory cells in the memory block to a pre-programmed state (Fig. 16: 1204); and
identifying a threshold voltage of the memory cells in the pre-programmed state (Fig. 16: 1206); and
after erasing the data in the memory block (Fig. 16: 1202) performing a next program operation of the first program operation to programing memory cells (Fig. 16: 1210-1216) in the memory block using at least one program pulse with a program voltage lower (para 90 “Vpgm(0)=Vpgm_nomimal-3(DAC)”) than a pre-defined program voltage (para 90 “Vpgm_nominal”) for the next program operation when the threshold voltage (para 90 “Vth_trial”) is higher than a pre-set voltage (para 90 “VtrH”).
Kamei fails to teach that the pre-program step and identification of threshold voltage step happen before the block is erased. However, applicant’s claims represent an obvious variant of Kamei’s. MPEP 2144.04(IV)(C) states “selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results.” It would be obvious variant to merely use a different program pulse adjusted to program cells from an erased state using threshold voltages measured after in a pre-program operation, rather than setting it based on programming from a pre-programmed state.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Kamei to produce the method of programming a memory consisting of a pre-programming step followed by a threshold voltage identification step, an erase step, and finally a programming step where the programming process uses the threshold voltages identified in preprogramming to program the cells.
Claims 4-7, 13-15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kamei et al (US 20080158980) and Prakash et al (US 20250061948)
Regarding Claim 4, Kamei teaches the limitations of Claim 1. Kamei teaches identifying the threshold voltage (Fig. 16: 1206) and applying a set of read voltages to the memory cells (para 106 “read operations can be performed at VtrL, VtrM, and VtrH,”)
Kamei fails determining failed bit counts in order to identify the threshold voltage.
Prakash however teaches determining a set of fail bit counts (FBCs) of the memory cells corresponding to the set of the read voltages (Fig. 1C: 162);
Counting the number of failed bits is useful because it allows to determine whether or not the program voltage needs to be adjusted using a simple binary of pass fail. From there if it is determined an adjustment needs to be made finer tuning can be can be done by sensing the threshold voltages to adjust the program voltage as desired in response to the threshold voltage sensed.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Prakash to the teachings of Kamei to produce a method of adjusting the threshold voltage that involves determining a set of failed bit counts.
Regarding Claim 5, Kamei and Prakash teaches the limitations of Claim 4. Prakash further teaches comparing the set of FBCs to a threshold (Fig. 1C: 162), wherein a FBC associated with a read voltage of the set of the read voltages that is identified as the threshold voltage is less than the threshold (Fig.1C: 163).
Regarding Claim 6, Kamei teaches the limitations of Claim 1. Kamei teaches wherein the at least one program pulse is a single program pulse, and wherein at least one of a program voltage of the single program pulse or a pulse length of the single program pulse is determined based on the threshold voltage (Fig. 16: 1208).
However, Kamei fails to teach singe level cells.
Prakash teaches single level cells (para 108 “In the SLC storage scheme, there are two total data states, including the erased state (Er) and a single programmed data state (S1).”).
Single level cells are an obvious variant from multilevel cells well understood to one of ordinary skill in the art. Programming of data can be much faster when each cell only needs to programmed to one state. It comes at a sacrifice of density but there are applications where that tradeoff is beneficial.
It would therefore have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Prakash to the teachings of Kamei to produce a memory that is programmed using the method outlined in claim 1 that consists of single level cells.
Regarding Claim 7, Kamei and Prakash teach the limitations of Claim 6. Kamei further teaches wherein the program voltage is lower than a pre-defined program voltage, wherein a difference between the pre-defined program voltage and the program voltage is positively correlated to a value of the threshold voltage (para 90 shows a series of equations where DAC values are subtracted from the Vpgm_nominal. This differs from Paragraph 91 where the equations show the same DAC value being added. From this it is understood given that “Vpgm_nominal is the standard magnitude of the first pulse without adjusting” that this means that the program voltage after adjustment can be lower than the pre-defined one.).
Regarding Claim 13, Kamei teaches the limitations of Claim 10.
Claim 13 is rejected for the same reasons as Claim 4.
Regarding Claim 14, Kamei teaches the limitations of Claim 10.
Claim 14 is rejected for the same reasons as Claim 6.
Regarding Claim 15, Kamei teaches the limitations of Claim 14.
Claim 15 is rejected for the same reasons as claim 7.
Regarding Claim 20, Kamei teaches the limitations of Claim 19.
Claim 20 is rejected for the same reasons as claim 7.
Claims 9 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kamei et al (US 20080158980) and Guo et al (US 20230154550).
Regarding Claim 9, Kamei teaches the limitations of Claim 1. Kamei fails to teach wherein a quantity of erase operations performed on the memory block is greater than a pre-determined threshold.
Guo teaches performing and additional erase operation beyond a predetermined threshold (para 122 “If the result (N2−N1) is greater than or equal to the Threshold, then an extra erase operation”)
Guo states the rationale for this is “ to reduce the threshold voltages of the memory cells of the edge word lines to align more closely with the threshold voltages of the other data word lines.” Thus, there would be an advantage in monitoring the threshold voltages of the cells and when a certain threshold of a number of cycles has been reached performing a greater quantity of Erase cycles than the threshold in order to produce a more uniform threshold distribution across the cells in the array.
It would have therefore been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to apply the teachings of Guo to the teachings of Kamei to produce a method of programming a memory where more erase cycles are performed than a pre-defined threshold.
Regarding Claim 17, Kamei teaches the limitations of Claim 10.
Claim 17 is rejected for the same reasons as Claim 9.
Response to Arguments
Applicant's arguments filed January 2, 2026 have been fully considered but they are not persuasive.
Applicant argues the obviousness rejection of claim 1 over the Kamei et al (US 20080158980) is improper because, according to applicant, Kamei does not disclose “using at least one program pulse with a program voltage lower than a pre-defined program voltage.”
Applicant correctly identifies paragraphs 90-91 as important to the claimed invention. Although applicant asserts paragraph 91's teaching of increasing the program voltage, to persuade that the claimed "program voltage lower than the predefined program voltage" is not met, applicant appears to have overlooked paragraph 90, which discloses decreasing the program voltage (i.e., Vpgm_nominal - DAC * offset).
Applicant additionally argues the differences between the claimed invention and the prior art would not have been obvious as a mere rearrangement of parts under MPEP 2144.04(VI)(C) because, according to applicant through argument of counsel, their claimed invention yields new and unexpected results.
This argument is not persuasive because applicant has not met their burden to establish new and unexpected results. For new and unexpected results, MPEP 716.02(b) provides the following instructions:
716.02(b) Burden on Applicant [R-08.2012][AltContent: rect]
I. BURDEN ON APPLICANT TO ESTABLISH RESULTS ARE UNEXPECTED AND SIGNIFICANT
The evidence relied upon should establish "that the differences in results are in fact unexpected and unobvious and of both statistical and practical significance." Ex parte Gelles, 22 USPQ2d 1318, 1319 (Bd. Pat. App. & Inter. 1992) (Mere conclusions in appellants’ brief that the claimed polymer had an unexpectedly increased impact strength "are not entitled to the weight of conclusions accompanying the evidence, either in the specification or in a declaration."); Ex parte C, 27 USPQ2d 1492 (Bd. Pat. App. & Inter. 1992) (Applicant alleged unexpected results with regard to the claimed soybean plant, however there was no basis for judging the practical significance of data with regard to maturity date, flowering date, flower color, or height of the plant.). See also In re Nolan, 553 F.2d 1261, 1267, 193 USPQ 641, 645 (CCPA 1977) and In re Eli Lilly, 902 F.2d 943, 14 USPQ2d 1741 (Fed. Cir. 1990) as discussed in MPEP § 716.02(c).
II. APPLICANTS HAVE BURDEN OF EXPLAINING PROFFERED DATA
"[A]ppellants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness." Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992).
III. DIRECT AND INDIRECT COMPARATIVE TESTS ARE PROBATIVE OF NONOBVIOUSNESS
Evidence of unexpected properties may be in the form of a direct or indirect comparison of the claimed invention with the closest prior art which is commensurate in scope with the claims. See In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980) and MPEP § 716.02(d) - § 716.02(e). See In re Blondel, 499 F.2d 1311, 1317, 182 USPQ 294, 298 (CCPA 1974) and In re Fouche, 439 F.2d 1237, 1241-42, 169 USPQ 429, 433 (CCPA 1971) for examples of cases where indirect comparative testing was found sufficient to rebut a prima facie case of obviousness.
The patentability of an intermediate may be established by unexpected properties of an end product "when one of ordinary skill in the art would reasonably ascribe to a claimed intermediate the ‘contributing cause’ for such an unexpectedly superior activity or property." In re Magerlein, 602 F.2d 366, 373, 202 USPQ 473, 479 (CCPA 1979). "In order to establish that the claimed intermediate is a ‘contributing cause’ of the unexpectedly superior activity or property of an end product, an applicant must identify the cause of the unexpectedly superior activity or property (compared to the prior art) in the end product and establish a nexus for that cause between the intermediate and the end product." Id. at 479.
Applicant has not satisfied their burden to establish new and unexpected results, but only presented argument of counsel. MPEP2145(I) states “Arguments presented by applicant cannot take the place of evidence in the record. See In re De Blauwe, 736 F.2d 699, 705, 222 USPQ 191, 196 (Fed. Cir. 1984); In re Schulze, 346 F.2d 600, 602, 145 USPQ 716, 718 (CCPA 1965); In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997) (‘An assertion of what seems to follow from common experience is just attorney argument and not the kind of factual evidence that is required to rebut a prima facie case of obviousness.’). See MPEP § 716.01(c) for examples of applicant statements which are not evidence and which must be supported by an appropriate affidavit or declaration.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JOSEPH FIDELIS STORMES/ Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/ Supervisory Patent Examiner, Art Unit 2825
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