DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendments to the claims entered 06/30/2026 have been considered by the examiner. The amendments overcome the previously presented 35 USC 102 (a)(1)/(a)(2) rejection.
Response to Arguments
Applicant’s arguments with respect to claims 1-4, 6-11 and 13-14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1-3, 6-10, 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Hietala et al. (US-20120306572-A1) hereinafter Hietala in view of Johnson (US-6812874-B1) and further in view of Waheed et al. (US-9020454-B2) hereinafter Waheed.
For examination purposes, claims 1-4 and 6-7 referring to an apparatus and claims 8-11 and 13-14 referring to a method are henceforth grouped together for claims mirroring the same limitations or which disclose analogous art to the invention as claimed.
Regarding Claims 1 and 8, Hietala discloses an indicator circuit, comprising: a power detection circuit, coupled to a signal output terminal of a transmitter circuit, and arranged to detect a power of an output signal to generate a detection result (Hietala, par. 36; A system for calibrating a non-linear power detector of a radio frequency device may use measurements of the non-linear power detector output and the associated RF power amplifier output level and a set of data points that characterizes a nominal non-linear power detector to calibrate the radio frequency device) and a codeword mapping circuit, arranged to generate an indicator codeword according to the detection result (Hietala, par. 69; The feedback circuit 124 may be in communication with the output circuit 122 and configured to receive an indication of the device output 132 of the electronic circuit 118 generated by the output circuit 122. The indication of the device output 132 of the electronic circuit 118 may be a voltage or a current. The indication of the device output 132 of the electronic circuit 118 may provide an indication of a power level delivered by the output circuit 122 to a load ), wherein the codeword mapping circuit converts the detection result according to a plurality of non-linear bases to correspondingly generate a plurality of converted detection results, and combines the plurality of converted detection results to generate the indicator codeword (Hietala, par. 36; The measured non-linear power detector outputs, measured power amplifier output levels, and the nominal power detector output data may be used to determine a power detector error function that characterizes the difference between the response of the non-linear power detector and the nominal non-linear power detector. The power detector error function and the nominal power detector output data may be used to develop a calibrated power detector output data set. The calibrated power detector output data may be stored in the non-linear power detector in order to calibrate the non-linear power detector). Examiner notes, Hietala inherently discloses the use of a “code word” as the measured output value to be processed for calibration as observed in figs. 3 and 5, where the calibrated output (VDET-CAL) is fed back to the transmitter control system, see par. 43. wherein the detection result is a binary value, the binary value comprises a plurality of bits, the plurality of bits comprise multiple first bits of a first number and multiple second bits of a second number, the multiple first bits at least comprise a most significant bit (MSB) in the plurality of bits, the multiple second bits at least comprise a least significant bit (LSB) in the plurality of bits; and when the codeword mapping circuit converts the detection result according to the plurality of non-linear bases, the codeword mapping circuit obtains a first value and a second value according to the multiple first bits, obtains a difference value between the first value and the second value, calculates an offset according to the multiple second bits and the difference value, and generates a corresponding converted detection result in the plurality of converted detection results according to the first value and the offset (Hietala, par 43; Each of the calibrated power detector outputs, V.sub.DET.sub.--.sub.CAL, represent a power detector output voltage, V.sub.DET, that the non-linear power detector 32 generates for a particular power amplifier output power level sensed by the RF coupler 16. The processor 24 may use the calibrated detector output data to set the value of the digital V.sub.RAMP signal, V.sub.RAMP.sub.--.sub.D, during operation of the RF device 10A)..
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Hietala does not explicitly disclose a method wherein the detection result is a binary value comprising a plurality of bits, the plurality of bits comprising multiple first bits of a first number and multiple second bits of a second number, the multiple first bits at least comprise a most significant bit (MSB) in the plurality of bits, the multiple second bits at least comprise a least significant bit (LSB) in the plurality of bits. However, Johnson discloses a method and apparatus for processing analog signals using a programable signal converted in which a mapping between input and output voltages is loaded into a mapping device (Johnson, par. 19; wherein the binary outputs are used to address the memory of the lookup table, thereby significantly speeding up the overall process), where the ADC calculates the output in a binary format (Johnson, par. 7; This output format blends well with successive-approximation ADCs since their internal architecture calculates each binary output bit from the most significant bit, one-by-one, down to the least significant bit. Binary formatting is a natural product of the successive-approximation algorithm).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine Hietala’s method for calibrating a power amplifier with Johnson’s methods for processing analog signals to enhance the speed of digital to analog conversion by mapping values to a look-up table
The combination of Hietala and Johnson does not explicitly disclose the generation of a codeword according to update the lookup table based on the plurality of converted detection results. However, in analogous art, Waheed discloses a linearization and calibration method for digital power amplifiers wherein the predistortion calibration method consist of performing multiple output samples (Waheed, fig. 15, col. 19, lines 20-40; The data is passed through the TX and then coupled in a controlled manner into the RX. The digitized RX output is then read as DRX_PRED_I and DRX_PRED_Q (step 376) …. the method repeats steps 376 through 384 until all N steps are sampled (i.e. the scan is complete)) and updating the LUT table based on samples taken (Waheed, fig. 15, col. 19, lines 20-40; Using the above computed predistortion error, the AM/AM and AM/PM predistortions are updated (step 392). For the AM/AM predistortion, the input to the LUT is the uncorrected ramp, i.e. N point DTX_PRED_RHO, while the output is the adjusted digital amplitude word DTX_PRED_RHO+PRED_ERR_RHO. For the AM/PM predistortion, the input to the LUT is the N point DTX_PRED_RHO applied, while the output is the PRED_ERR_THETA measured as a result of the above measurements) see also fig. 11.
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Therefore it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine, Hietala’s method for calibrating a power amplifier with Johnson’s methods for processing analog signals and Waheeds teachings for calibrating power amplifiers to enhance linearity and accuracy of transmitter output signals.
Regarding Claims 2 and 9, the combination of Hietala, Johnson and Waheed further discloses the method and apparatus of claims 1 and 8; wherein the power of the output signal has a non-linear corresponding relationship with the detection result, the detection result has a non-linear corresponding relationship with the indicator codeword, and the power of the output signal has a linear corresponding relationship with the indicator codeword (Hietala, fig. 3 par. 53; The memory of the calibration controller 42A may include nominal power detector output data. The nominal power detector output data represents the expected nominal input-output relationship of a nominal non-linear power detector of a nominal RF device 44A. FIG. 3 depicts a nominal power detector curve (solid line) that may be generated based upon the nominal power detector output data. The nominal power detector curve (solid line) may include a nominal power detector output voltage, VNOM (VOUT), of FIG. 3, for each output power level that the RF device 44A is expected to generate … The relationship between the nominal power detector output voltage, VNOM (VOUT — NOM), and the nominal power amplifier output levels, VOUT — NOM, provide the nominal power detector curve (solid line) and represent an expected performance of the non-linear power detector of the RF device 44A).
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Regarding Claims 3 and 10, the combination of Hietala, Johnson and Waheed further discloses the method and apparatus of claims 1 and 8, wherein when the power of the output signal changes, a value corresponding to the indicator codeword changes correspondingly in a linear manner (Hietala, fig. 1C, par. 46; The processor 24 uses the digital power detector output voltage signal, V.sub.DET.sub.--.sub.D, to determine a difference between the sensed RF.sub.OUT signal 34 and a desired output power level of the RF power amplifier 14. The processor 24 then changes the value of the digital power detector output voltage signal, V.sub.DET.sub.--.sub.D, to minimize the difference between the sensed RF.sub.OUT signal 34 and a desired output power level of the RF power amplifier 14) see also waheed figs. 11 and 15.
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Regarding Claims 6 and 13, the combination of Hietala, Johnson and Waheed further discloses invention according to claims 1 and 8, wherein the first value is directly related to the first number of first bits (Johnson, par. 7; This output format blends well with successive-approximation ADCs since their internal architecture calculates each binary output bit from the most significant bit, one-by-one, down to the least significant bit. Binary formatting is a natural product of the successive-approximation algorithm), and the first value and the second value are set according to a corresponding non-linear basis in the plurality of non-linear bases (Johnson, par. 39; An apparatus for reading or modifying data comprising: a level detector having an analog input to receive an analog voltage of an analog signal and having a plurality of outputs … wherein said active output of the plurality of outputs of the logic stage is used to address one of the plurality of locations in the first table and thereby read a mapping value stored therein; and a second table including a plurality of locations storing a plurality of address values, each address value of which is indicative of a relative position in the second table in which said each address value is stored, wherein said relative position in the second table also correspond to a value of the analog voltage used to address the first table, said second table having an output outputting an address value stored in a location of the plurality of locations being addressed by the active output of the plurality of outputs of the logic stage) see also Waheed figs. 8 and 11.
Regarding Claims 7 and 14, the combination of Hietala, Johnson and Waheed further discloses invention according to claims 1 and 8, wherein the codeword mapping circuit comprises one or more lookup tables (Johnson, par. 16; input-to-output mapping device 83 includes a lookup table (LUT) stored in memory whose stored values are addressed by read signals connected to each read location individually. The outputs of these boundary detection gates connect directly to the input-to-output mapping device), one of the one or more lookup tables corresponds to one of the plurality of non-linear bases, the one or more lookup tables comprise a plurality of elements, respectively, and a number of the plurality of elements is determined according to the first number Waheed, fig. 8, col. 15 lines 6-13; The samples of the converted signal are compared against the corresponding nominal amplitude and phase to determine the amplitude-dependent distortion and accordingly update the digital predistortion mechanisms, including the predistortion LUT 226, to ensure good RF linearization characteristics across PVT and frequency).
Claim 4 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Hietala et al. (US-20120306572-A1) hereinafter Hietala in view of Johnson (US-6812874-B1), in view of Waheed et al. (US-9020454-B2) hereinafter Waheed and further in view of Braithwaite (US-20050190857-A1).
Regarding Claims 4 and 11 the combination of Hietala, Johnson and Waheed further discloses the method and apparatus of claims 1 and 8, wherein the plurality of non-linear bases are bases of different orders (Hietala, par. 59; the calibration controller 42A may provide a value of a target supply voltage for each of the plurality of power amplifier output levels to be generated by the power amplifier of the RF device).
The combination of hietala, Johnson and Waheed does not explicitly teach the plurality of non-linear bases being of multiple orders, however, Braithwaite discloses a system for linearizing FR amplifiers employing baseband predistortion techniques providing (Braithwaite, par. 27; the memory DPD operation is based on a polynomial model of the nonlinearity and the memoryless DPD is (preferably) implemented using look-up tables that map the power amplifier gain corrections to the input signal magnitude (or power). Separating the memoryless and memory DPD circuits allows the use of different structures or different orders of nonlinear correction).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine Hietala’s method for calibrating a power amplifier with Johnson’s methods for processing analog signals with Waheeds teachings for calibrating power amplifiers and Braithwaite’s system for linearizing an RF power amplifier to enhance the calibration accuracy in nonlinear RF power amplifiers.
It is noted that any citations to specific pages, columns, lines or figures in the prior art
references and any interpretation of the reference should not be considered limiting in any way. A
reference is relevant for all it contains and may be relied upon for all that it would have reasonably
suggested to a person of ordinary skill in the art. See MPEP 2123
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Other Relevant Prior Art Not relied Upon
Hahn et al. (US-8615207-B2) Power amplifier linearization feedback methods and systems, 2013. Linearizers can improve the linearity of power amplifiers by canceling or reducing amplitude of non-linearity components, (e.g., IM3, IM5, IM7, IM9, etc.) generated by the power amplifier. The linearizers can obtain samples of signals output by the power amplifier and process the samples to produce a compensation signal that is applied onto or into a transmission path leading to the power amplifier's input. The compensation signal is generated such that when amplified by the power amplifier, the amplified compensation signal cancels or reduces at least a portion of the non-linearity components produced by the power amplifier. A controller can improve the correction of the non-linearity components by executing one or more calibration algorithms and/or one or more tuning algorithms and adjusting settings of the linearizer based on the results of the algorithm(s).
Agi (US-8564463-B2) Integrated Non-Linearity (INL) and Differential Non-Linearity (DNL) correction techniques for digital-to-analog converters (DACS), 2013. INL values are determined for sub-segments of a DAC adapted to accept N bit digital input codes, and a first set of correction codes that can be used to reduce to a range of INL values (to improve linearity of the DAC) are determined and stored. Additionally, DNL values are determined for the sub-segments of the DAC, and a second set of correction codes that can be used to ensure that all values of DNL>−1 (to ensure that the DAC is monotonic) are determined and stored. This can include using one or more extra bits of resolution to remap at least some of the 2^N possible digital input codes (that can be accepted by the DAC) to more than 2^N possible digital output codes, to ensure that all values of DNL>−1. Such stored first and second sets are thereafter used when performing digital to analog conversions.
Yong Fang (arXiv:1010.3150) Application of DAC Codeword Spectrum: Expansion Factor, 2010. Distributed Arithmetic Coding (DAC) proves to be an effective implementation of Slepian-Wolf Coding (SWC), especially for short data blocks. To study the property of DAC codewords, the author has proposed the concept of DAC codeword spectrum. For equiprobable binary sources, the problem was formatted as solving a system of functional equations. Then, to calculate DAC codeword spectrum in general cases, three approximation methods have been proposed. In this paper, the author makes use of DAC codeword spectrum as a tool to answer an important question: how many (including proper and wrong) paths will be created during the DAC decoding, if no path is pruned? The author introduces the concept of another kind of DAC codeword spectrum, i.e. time spectrum, while the originally-proposed DAC codeword spectrum is called path spectrum from now on. To measure how fast the number of decoding paths increases, the author introduces the concept of expansion factor which is defined as the ratio of path numbers between two consecutive decoding stages. The author reveals the relation between expansion factor and path/time spectrum, and proves that the number of decoding paths of any DAC codeword increases exponentially as the decoding proceeds. Specifically, when symbols `0' and `1' are mapped onto intervals [0, q) and [(1-q), 1), where 0.5<q<1, the author proves that expansion factor converges to 2q as the decoding proceeds.
Choi et al. (US-9748912-B2), Method and apparatus for detecting power, 2017. Provided is a Radio Frequency (RF) communication apparatus and a method for detecting power. The RF communication apparatus includes a receiver that receives a segment value indicating one of multiple transmission output power ranges, a power detector that detects a strength of an RF transmission signal in an output power range corresponding to the segment value, and a transmitter that transmits the strength of the detected RF transmission signal. The power detector includes a feedback unit that receives the fed-back RF transmission signal, an RF core unit that generates a Root Mean Square (RMS) of the RF transmission signal, and a converter that converts a current signal corresponding to the RMS of the RF transmission signal into a voltage signal, and converts the converted voltage signal from a differential signal to a single signal.
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/MARIO R CAMPERO MIRAMONTES/Examiner, Art Unit 2649 /YUWEN PAN/Supervisory Patent Examiner, Art Unit 2649
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