DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Claims 1-20 are pending and have been examined.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1-2 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Shim et al. (US 20220013464 A1 – hereinafter Shim) in view of Lin (US 20150001708 A1) and Takahashi (US 20110309523 A1).
Regarding independent claim 1, Shim teaches:
A semiconductor package (1000 – Fig. 1 – [0025] – “semiconductor
package 1000”) comprising:
a first package substrate (101 – Fig. 1 – [0025] – “first package substrate
101”);
a first semiconductor chip (130 – Fig. 1 – [0025] – “first semiconductor chip
130”) on the first package substrate (101);
an interposer (200 – Fig. 1 – [0025] – “interposer 200”) on the first
semiconductor chip (130);
a support substrate on the first package substrate, the support substrate being
spaced apart from a sidewall of the first semiconductor;
a conductive filler on the support substrate;
a connection bump between the support substrate and the interposer (200), the connection bump configured to electrically connect the conductive filler with the interposer (200); and
a first molding layer (170 – Fig. 1 – [0041] – “insulating filler 170 may cover an upper surface of the first package substrate 101, a side wall and an upper surface of the first semiconductor chip 130, a side wall of the substrate-interposer conductive connector 160” – this corresponds to molding layer) configured to surround the sidewall of the first semiconductor chip (130) and a sidewall of the connection bump (160 – Fig. 1 – [0041] – “the substrate-interposer conductive connector 160” – this correspond to the connection bump).
Shim does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Lin teaches
a support substrate (144 – Fig. 11 – [0099] – “insulating layer 144” – this
corresponds to a support substrate) on the first package substrate (190 – Fig. 11 – [0078] – “build-up interconnect structure 190” – this corresponds to the first package substrate), the support substrate (144) being spaced apart from a sidewall of the first semiconductor chip (124 – [0093] – “semiconductor die 124” – Fig. 11 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the support substrate structure as taught by Lin into Shim.
An ordinary artisan would have been motivated to use the known technique of Lin in the manner set forth above to produce the predictable results of [0010] – “a fan-out package-on-package (Fo-PoP) having a reduced package height and fine-pitch vertical interconnections” that is not susceptible to issues [0009] – “of a conventional substrate leads to warpage and reduced thermal performance. Further, substrates having a thickness of 130 .mu.m or less cause problems during handling, particularly during a pick and place operation. Thin package substrates are susceptible to damage and result in high cost processing.”
Shim and Lin do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Takahashi teaches
a conductive filler (232 – Fig. 4B – [0026] – “top metal land pads 232 on a top side of the interposer substrate”) on the support substrate (235 – Fig. 4B – [0026] – “interposer substrate 235” – this corresponds to a support substrate);
a connection bump (Fig. 4B annotated, see below – [0007] – “the interposer height is set so that the height of the solder ball (or other bonding conductor) used to bond the packaged IC” – hereinafter ‘223’) between the support substrate (235) and the interposer.
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive filler and bump structure as taught by Takahashi into Shim and Lin.
An ordinary artisan would have been motivated to use the known technique of Takahashi in the manner set forth above to produce the predictable results of [0008] – “Using a tunable interposer thickness, conventional package substrates (e.g., conventional planar printed circuit boards (PCBs)) can be used, and the processing is generally simplified and/or assembly costs reduced.”
Regarding claim 2, Shim as modified by Lin and Takahashi, teaches claim 1 from which claim 2 depends. Shim further teaches
wherein a bottom surface of the interposer (200) is spaced apart from
a top surface of the first semiconductor chip (130 – Fig. 1 shows this), and
the first molding layer (170) is configured to fill at least a portion of a gap ([0041] – “insulating filler 170 may cover an upper surface of the first package substrate 101, a side wall and an upper surface of the first semiconductor chip 130, a side wall of the substrate-interposer conductive connector 160, and the lower surface 209 of the interposer substrate 201”) between the top surface of the first semiconductor chip (130) and the bottom surface of the interposer (200 – Fig. 1 shows this).
Regarding claim 9, Shim as modified by Lin and Takahashi, teaches claim 1 from which claim 9 depends. Shim further teaches
comprising:
a second package substrate (400U – Fig. 13 – [0082] – “upper package 400U”)
on the interposer (200 – Fig. 13 shows this);
a second semiconductor chip (330 – Fig. 13 – [0086] – “second semiconductor
chip 330”) on the second package substrate (311 – Fig.13 – [0084] – “second package substrate 301 may include a substrate base 311”); and
a second molding layer (345 – Fig. 13 – [0088] – “molding layer 345 may be
disposed on the second package substrate 301 to cover at least a part of the second semiconductor chip 330”) configured to surround a sidewall of the second
semiconductor chip (330).
Regarding claim 10, Shim as modified by Lin and Takahashi, teaches claim 1 from which claim 10 depends. Shim and Lin do not expressly disclose the limitations of claim 10.
However, in an analogous art, Takahashi teaches
wherein
the support substrate (235) includes:
a support substrate base (235 – this is also the base of the support substrate); and
a conductive via (233 – Fig. 4A – [0026] – “vias 233”) configured to
pass through the support substrate base (235 – Fig. 4A shows this) and to electrically connect the conductive filler (232) with the first package substrate (205 – Fig. 4A – [0023] – “substrate 205”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the support base and via structure as taught by Takahashi into Shim and Lin.
An ordinary artisan would have been motivated to use the known technique of Takahashi in the manner set forth above to produce the predictable results as stated above in claim 1.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Shim in view of Lin, Takahashi, and Tseng et al. (US 20140264268 A1 – hereinafter Tseng).
Regarding claim 3, Shim as modified by Lin and Takahashi, teaches claim 1 from which claim 3 depends. Shim, Lin, and Takahashi do not expressly disclose the limitations of claim 3.
However, in an analogous art, Tseng teaches
wherein a surface roughness of a top surface of the first semiconductor
chip (160 – [0097] – “chip 160”) is greater than a surface roughness of the sidewall of the first semiconductor chip (160 – [0097] – “the top surface 851 has a surface topography variation of about +/-50 microns, whereas the side surfaces 850 has a surface topography variation of about +/-5 microns” – this is interpreted that the top surface is rougher than the side surface).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the surface structure as taught by Tseng into Shim, Lin, and Takahashi.
An ordinary artisan would have been motivated to use the known technique of Tseng in the manner set forth above to produce the predictable results [0002] – “to the fabrication of phosphor-coated light-emitting diode (LED) dies” where the rough surfaces allow better adhesion of follow on coatings.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Shim in view of Lin, Takahashi, and Talledo et al. (US 20160183369 A1 – hereinafter Talledo).
Regarding claim 4, Shim as modified by Lin and Takahashi, teaches claim 1 from which claim 4 depends. Shim, Lin, and Takahashi do not expressly disclose the limitations of claim 4.
However, in an analogous art, Talledo teaches
wherein the connection bump (48 – Fig. 2A – [0024] – “the conductive bumps
48 may be the same as the filler material 32 or may be a different material”) includes a material different from a material of the conductive filler (32 – Fig. 2A – [0024] – “the conductive bumps 48 may be the same as the filler material 32 or may be a different material”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the connection bump structure as taught by Talledo into Shim, Lin, and Takahashi.
An ordinary artisan would have been motivated to use the known technique of Talledo in the manner set forth above to produce the predictable results of [0007] – “a leadframe package with recesses formed in outer surface of the leads. The recesses are filled with a filler material, such as solder. The filler material in the recesses provides a wetable surface for filler material, such as solder, to adhere to during mounting of the package to another device, such as a printed circuit board (PCB). This enables strong solder joints between the leads of the package and the PCB. It also enables improved visual inspection of the solder joints after the package has been mounted.”
Claims 5, 11-13, and 15-20 is rejected under 35 U.S.C. 103 as being unpatentable over Shim in view of Lin, Takahashi, and Chen et al. (US 20240047322 A1 – hereinafter Chen).
Regarding claim 5, Shim as modified by Lin and Takahashi, teaches claim 1 from which claim 5 depends. Shim, Lin, and Takahashi do not expressly disclose the limitations of claim 5.
However, in an analogous art, Chen teaches
wherein the connection bump (12 – Fig. 4A – [0033] – “the conductive joint 12
substantially covers the entirety of the lower surface of the UBM pad 124AP which is exposed by the resist sublayer 124AR and also substantially covers the entireties of the upper surface and the sidewall of the conductive pads 1112ap”) is configured to surround a sidewall and a top surface of the conductive filler (1112ap – Fig. 4A – [0033] – “conductive pads 1112ap” – this corresponds to the conductive filler).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the connection bump structure as taught by Chen into Shim, Lin, and Takahashi.
An ordinary artisan would have been motivated to use the known technique of Chen in the manner set forth above to produce the predictable results of creating good conducting electrical connections.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding independent claim 11, Shim teaches:
A semiconductor package (1000 – Fig. 1 – [0025] – “semiconductor
package 1000”) comprising:
a first package substrate (101 – Fig. 1 – [0025] – “first package substrate
101”);
a first semiconductor chip (130 – Fig. 1 – [0025] – “first semiconductor chip
130”) on the first package substrate (101); an interposer (200 – Fig. 1 – [0025] – “interposer 200”) on the first semiconductor chip (130);
a heat transfer material layer configured to fill at least a portion of a gap between
a bottom surface of the interposer and a top surface of the first semiconductor chip;
a support substrate on the first package substrate, the support substrate being
spaced apart from a sidewall of the first semiconductor chip;
a conductive filler on the support substrate;
a connection bump between the support substrate and the interposer (200), the
connection bump configured to surround a sidewall and a top surface of the conductive filler; and
a first molding layer (170 – Fig. 1 – [0041] – “insulating filler 170 may cover an upper surface of the first package substrate 101, a side wall and an upper surface of the first semiconductor chip 130, a side wall of the substrate-interposer conductive connector 160” – this corresponds to molding layer) configured to surround the sidewall of the first semiconductor chip (130) and a sidewall of the connection bump (160 – Fig. 1 – [0041] – “the substrate-interposer conductive connector 160” – this correspond to the connection bump).
Shim does not expressly disclose the other limitations of claim 11.
However, in an analogous art, Lin teaches
a heat transfer material layer (262 – Fig. 12 – [0097] – “protection layer 262 is
selected to have good thermal conductivity”) configured to fill at least a portion of a gap ([0097] – ‘composite protection layer 262 is formed over supporting substrate 260. Protection layer 262 is a die attach adhesive, epoxy, or other adhesive material”)
between a bottom surface of the interposer (238 – [0094] – “interposer 238”) and a top surface of the first semiconductor chip (124 – [0093] – “semiconductor die 124”);
a support substrate (144 – Fig. 11 – [0099] – “insulating layer 144” – this
corresponds to a support substrate) on the first package substrate (190 – Fig. 11 – [0078] – “build-up interconnect structure 190” – this corresponds to the first package substrate), the support substrate (144) being spaced apart from a sidewall of the first semiconductor chip (124 – Fig. 12 – [0093] – “semiconductor die 124” – Fig. 11 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the support substrate structure as taught by Lin into Shim.
An ordinary artisan would have been motivated to use the known technique of Lin in the manner set forth above to produce the predictable results as stated above in claim 1.
Shim and Lin do not expressly disclose the other limitations of claim 11.
However, in an analogous art, Takahashi teaches
a conductive filler (232 – Fig. 4B – [0026] – “top metal land pads 232 on a top side of the interposer substrate”) on the support substrate (235 – Fig. 4B – [0026] – “interposer substrate 235” – this corresponds to a support substrate);
a connection bump (Fig. 4B annotated, see below – [0007] – “the interposer
height is set so that the height of the solder ball (or other bonding conductor) used to bond the packaged IC” – hereinafter ‘223’) between the support substrate (235).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive filler and bump structure as taught by Takahashi into Lin into Shim.
An ordinary artisan would have been motivated to use the known technique of Takahashi in the manner set forth above to produce the predictable results as stated above in claim 1.
Shim, Lin, and Takahashi do not expressly disclose the limitations of claim 11.
However, in an analogous art, Chen teaches
the connection bump (12 – Fig. 4A – [0033] – “the conductive joint 12
substantially covers the entirety of the lower surface of the UBM pad 124AP which is exposed by the resist sublayer 124AR and also substantially covers the entireties of the upper surface and the sidewall of the conductive pads 1112ap”) configured to surround a sidewall and a top surface of the conductive filler (1112ap – Fig. 4A – [0033] – “conductive pads 1112ap” – this corresponds to the conductive filler).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the connection bump structure as taught by Chen into Shim, Lin, and Takahashi.
An ordinary artisan would have been motivated to use the known technique of Chen in the manner set forth above to produce the predictable results as stated above in claim 5.
Regarding claim 12, Shim as modified by Lin, Takahashi, and Chen, teaches claim 11 from which claim 12 depends. Shim, Takahashi, and Chen do not expressly disclose the limitations of claim 12.
However, in an analogous art, Lin teaches
wherein the first molding layer (186 – Fig. 12 – [0076] – “Encapsulant 186 can
be polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler” – this corresponds to a molding layer) is configured to surround a sidewall of the heat transfer material layer (262).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the molding layer structure as taught by Lin into Shim, Takahashi, and Chen.
An ordinary artisan would have been motivated to use the known technique of Lin in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 13, Shim as modified by Lin, Takahashi, and Chen, teaches claim 11 from which claim 13 depends. Shim, Takahashi, and Chen do not expressly disclose the limitations of claim 13.
However, in an analogous art, Lin teaches
wherein
a sidewall of the heat transfer material layer (262) is spaced apart from the
sidewall of the connection bump (254 – Fig. 12 – [0095] – “Bumps 202 and 254 are reflowed at the same time to electrically connect Fo-PoP 230 to semiconductor device 234 and to substrate 252”), and
the first molding layer (186) is configured to fill at least a portion of a gap between the sidewall of the heat transfer material layer (262) and the sidewall of the connection bump (254).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the heat transfer layer structure as taught by Lin into Shim, Takahashi, and Chen.
An ordinary artisan would have been motivated to use the known technique of Lin in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 15, Shim as modified by Lin, Takahashi, and Chen, teaches claim 11 from which claim 15 depends. Shim, Takahashi, and Chen do not expressly disclose the limitations of claim 15.
However, in an analogous art, Lin teaches
wherein
the heat transfer material layer (262) includes at least one of a thermal
conductive adhesive tape, thermal conductive grease, a thermal conductive interface pad, or a thermal conductive adhesive ([0097] – ‘composite protection layer 262 is formed over supporting substrate 260. Protection layer 262 is a die attach adhesive, epoxy, or other adhesive material”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the heat transfer layer structure as taught by Lin into Shim, Takahashi, and Chen.
An ordinary artisan would have been motivated to use the known technique of Lin in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 16, Shim as modified by Lin, Takahashi, and Chen, teaches claim 11 from which claim 16 depends. Shim further teaches
comprising:
a second package substrate (400U – Fig. 13 – [0082] – “upper package 400U”)
on the interposer (200 – Fig. 13 shows this);
a second semiconductor chip (330 – Fig. 13 – [0086] – “second semiconductor
chip 330”) on the second package substrate (311 – Fig.13 – [0084] – “second package substrate 301 may include a substrate base 311”); and
a second molding layer (345 – Fig. 13 – [0088] – “molding layer 345 may be
disposed on the second package substrate 301 to cover at least a part of the second semiconductor chip 330”) configured to surround a sidewall of the second
semiconductor chip (330).
Regarding independent claim 17, Shim teaches:
A semiconductor package (1000 – Fig. 1 – [0025] – “semiconductor
package 1000”) comprising:
a first package substrate (101 – Fig. 1 – [0025] – “first package substrate
101”);
a first semiconductor chip (130 – Fig. 1 – [0025] – “first semiconductor chip
130”) on the first package substrate (101); an interposer (200 – Fig. 1 – [0025] – “interposer 200”) on the first semiconductor chip (130);
a heat transfer material layer configured to fill at least a portion of a gap between
a bottom surface of the interposer and a top surface of the first semiconductor chip;
a support substrate on the first package substrate, the support substrate being
spaced apart from a sidewall of the first semiconductor chip;
a conductive filler on the support substrate;
a connection bump between the support substrate and the interposer (200), is
configured to surround a sidewall and a top surface of the conductive filler and to electrically connect the conductive filler with the interposer (200);
a first molding layer (170 – Fig. 1 – [0041] – “insulating filler 170 may cover an upper surface of the first package substrate 101, a side wall and an upper surface of the first semiconductor chip 130, a side wall of the substrate-interposer conductive connector 160” – this corresponds to molding layer) configured to surround the sidewall of the first semiconductor chip (130) and a sidewall of the connection bump (160 – Fig. 1 – [0041] – “the substrate-interposer conductive connector 160” – this correspond to the connection bump), the first molding layer (170) being in contact with at least a portion of the sidewall of the connection bump (160);
a second package substrate (400U – Fig. 13 – [0082] – “upper package 400U”)
on the interposer (200 – Fig. 13 shows this);
a second semiconductor chip (330 – Fig. 13 – [0086] – “second semiconductor
chip 330”) on the second package substrate (311 – Fig.13 – [0084] – “second package substrate 301 may include a substrate base 311”); and
a second molding layer (345 – Fig. 13 – [0088] – “molding layer 345 may be
disposed on the second package substrate 301 to cover at least a part of the second semiconductor chip 330”) configured to surround a sidewall of the second
semiconductor chip (330).
Shim does not expressly disclose the other limitations of claim 11.
However, in an analogous art, Lin teaches
a heat transfer material layer (262 – Fig. 12 – [0097] – “protection layer 262 is
selected to have good thermal conductivity”) configured to fill at least a portion of a gap ([0097] – ‘composite protection layer 262 is formed over supporting substrate 260. Protection layer 262 is a die attach adhesive, epoxy, or other adhesive material”)
between a bottom surface of the interposer (238 – [0094] – “interposer 238”) and a top surface of the first semiconductor chip (124 – [0093] – “semiconductor die 124”);
a support substrate (144 – Fig. 11 – [0099] – “insulating layer 144” – this
corresponds to a support substrate) on the first package substrate (190 – Fig. 11 – [0078] – “build-up interconnect structure 190” – this corresponds to the first package substrate), the support substrate (144) being spaced apart from a sidewall of the first semiconductor chip (124 – Fig. 12 – [0093] – “semiconductor die 124” – Fig. 11 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the heat transfer and support substrate structure as taught by Lin into Shim.
An ordinary artisan would have been motivated to use the known technique of Lin in the manner set forth above to produce the predictable results as stated above in claim 1.
Shim and Lin do not expressly disclose the other limitations of claim 11.
However, in an analogous art, Takahashi teaches
a conductive filler (232 – Fig. 4B – [0026] – “top metal land pads 232 on a top side of the interposer substrate”) on the support substrate (235 – Fig. 4B – [0026] – “interposer substrate 235” – this corresponds to a support substrate).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive filler structure as taught by Takahashi into Shim and Lin.
An ordinary artisan would have been motivated to use the known technique of Takahashi in the manner set forth above to produce the predictable results as stated above in claim 1.
Shim, Lin, and Takahashi do not expressly disclose the limitations of claim 11.
However, in an analogous art, Chen teaches
a connection bump (12 – Fig. 4A – [0033] – “the conductive joint 12
substantially covers the entirety of the lower surface of the UBM pad 124AP which is exposed by the resist sublayer 124AR and also substantially covers the entireties of the upper surface and the sidewall of the conductive pads 1112ap”) between the support substrate and the interposer, is configured to surround a sidewall and a top surface of the conductive filler (1112ap – Fig. 4A – [0033] – “conductive pads 1112ap” – this corresponds to the conductive filler) and to electrically connect the conductive filler (1112ap) with the interposer;
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the connection bump structure as taught by Chen into Shim, Lin, and Takahashi.
An ordinary artisan would have been motivated to use the known technique of Chen in the manner set forth above to produce the predictable results as stated above in claim 5.
Regarding claim 18, Shim as modified by Lin, Takahashi, and Chen, teaches claim 17 from which claim 18 depends. Shim further teaches
wherein
a bottom surface of the interposer (200) is spaced apart from a top surface
of the first semiconductor chip (130 – Fig. 13 shows this), and
the first molding layer (170) is configured to fill at least a portion of a gap between the top surface of the first semiconductor chip (130) and the bottom surface of the interposer (200 – Fig. 13 shows this).
Regarding claim 19, Shim as modified by Lin, Takahashi, and Chen, teaches claim 17 from which claim 19 depends. Shim, Takahashi, and Chen do not expressly disclose the limitations of claim 19.
However, in an analogous art, Lin teaches
wherein
a bottom surface of the interposer (238 – [0094] – “interposer 238”) is spaced
apart from a top surface of the first semiconductor chip (124 – [0093] – “semiconductor die 124”), and
the semiconductor package comprises a heat transfer material layer (262 – Fig. 12 – [0097] – “protection layer 262 is selected to have good thermal conductivity”) configured to fill at least a portion of a gap between the top surface of the first semiconductor chip (124) and the bottom surface of the interposer (238).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the interposer and heat transfer layer structure as taught by Lin into Shim, Takahashi, and Chen.
An ordinary artisan would have been motivated to use the known technique of Lin in the manner set forth above to produce the predictable results as stated above in claim 1.
Regarding claim 20, Shim as modified by Lin, Takahashi, and Chen, teaches claim 17 from which claim 20 depends. Shim, Lin, and Chen do not expressly disclose the limitations of claim 20.
However, in an analogous art, Takahashi teaches
wherein
the support substrate (235) includes:
a support substrate base (235 – this is also the base of the support substrate); and
a conductive via (233 – Fig. 4A – [0026] – “vias 233”) configured to
pass through the support substrate base (235 – Fig. 4A shows this) and to electrically connect the conductive filler (232) with the first package substrate (205 – Fig. 4A – [0023] – “substrate 205”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive filler structure as taught by Takahashi into Shim, Lin, and Chen.
An ordinary artisan would have been motivated to use the known technique of Takahashi in the manner set forth above to produce the predictable results as stated above in claim 1.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Shim in view of Lin, Takahashi, and Lee et a. (US 20210028146 A1 – hereinafter Lee).
Regarding claim 6, Shim as modified by Lin and Takahashi, teaches claim 1 from which claim 6 depends. Shim, Lin, and Takahashi do not expressly disclose the limitations of claim 6.
However, in an analogous art, Lee teaches
wherein
the first molding layer ([0025] – “molding parts 400 and 600” – this is
correspond to the first molding layer, hereinafter ‘MD1’) includes a lower molding layer (400 – Fig. 2 – [0033] – “first molding part 400”) and an upper molding layer (600 – Fig. 2 – [0040] – “second molding part 600 is provided on the first molding part 400”),
each molding layer of the lower molding layer (400) and the upper molding layer (600) includes at least one of an epoxy molding compound (EMC), a filler, or a hardener, and
a ratio of the EMC, the filler, and the hardener in the lower molding layer (400 – [0033] – “first molding part 400 may include an insulating material having high machinability, such as polyimide” – a polyamide is an epoxy) is different (600 – [0040] – “A coefficient of thermal expansion of the second molding part 600 may be different from a coefficient of thermal expansion of the first molding part 400 (for example, it may be greater, or it may be less)” – this is interpreted as having different ratios) from a ratio of the EMC, the filler, and the hardener in the upper molding layer (600 – [0040] – “the second molding part 600 may include an epoxy molding compound (EMC)”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the molding layer structure as taught by Lee into Shim, Lin, and Takahashi.
An ordinary artisan would have been motivated to use the known technique of Lee in the manner set forth above to produce the predictable results to [0006] – “provide a semiconductor package with improved structural stability and a method for manufacturing the same.”
Claims 7-8 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Shim in view of Lin, Takahashi, Chen, and Yim et al. (US 20210183777 A1 – hereinafter Yim).
Regarding claim 7, Shim as modified by Lin, Takahashi, and Chen, teaches claim 1 from which claim 7 depends. Shim, Lin, and Takahashi do not expressly disclose the limitations of claim 7.
However, in an analogous art, Chen teaches
the conductive filler (1112ap).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive filler structure as taught by Chen into Shim, Lin, and Takahashi.
An ordinary artisan would have been motivated to use the known technique of Chen in the manner set forth above to produce the predictable results as stated above in claim 5.
Shim, Lin, Takahashi, and Chen do not expressly disclose the other limitations of claim 7.
However, in an analogous art, Yim teaches
wherein
the first molding layer (140 and 200 combined Fig. 2 – [0041] – “insulating filler
220 may be formed of under-fill resin formed by a capillary under-fill method. Alternatively, in example embodiments, the insulating filler 220 may be a non-conductive film. In example embodiments, the insulating filler 220 may include a material different from that of the first molding layer 140” – this compares 220 to molding layer 140, thus 220 is interpreted as the first molding layer, hereinafter ‘FML’) includes:
a lower molding layer (140 – Fig. 2- [0038] – “through holes 141 of the first molding layer 140”) defining a recess (141 – Fig. 2 – [0038] – “through holes 141 of the first molding layer 140”); and
an upper molding layer (221 – Fig. 2 – [0038] – “first portion 221 of the insulating filler 220 may fill a gap between side walls of the conductive connectors 210 and an inner wall of the first molding layer 140 provided by the through holes 141 of the first molding layer 140”) configured to fill at least a
portion of the recess (141), and the conductive filler is positioned at the recess (141).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the molding layer structure as taught by Yim into Shim, Lin, and Takahashi.
An ordinary artisan would have been motivated to use the known technique of Yim in the manner set forth above to produce the predictable results of [0029] – “The first molding layer 140 may protect the first semiconductor chip 120 against an external environment. In addition, the first molding layer 140 may include an under-fill portion that fills a gap between the first semiconductor chip 120 and the first package substrate 110 and surrounds the chip connection terminals 131 interposed between the first semiconductor chip 120 and the first package substrate 110.”
Regarding claim 8, Shim as modified by Lin, Takahashi, and Chen, teaches claim 1 from which claim 8 depends. Shim, Lin, and Takahashi do not expressly disclose the limitations of claim 8.
However, in an analogous art, Chen teaches
the conductive filler (1112ap) and the connection bump (12).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the conductive filler and connection bump structure as taught by Chen into Shim, Lin, and Takahashi.
An ordinary artisan would have been motivated to use the known technique of Chen in the manner set forth above to produce the predictable results as stated above in claim 5.
Shim, Lin, Takahashi, and Chen do not expressly disclose the other limitations of claim 7.
However, in an analogous art, Yim teaches
wherein
the first molding layer (FML) includes:
a lower molding layer (140) defining a recess (141) including a first portion and a second portion; and
an upper molding layer (220) on the lower molding layer (140),
the conductive filler and the connection bump are filled with the first
portion of the recess (141), and
the upper molding layer (220) is configured to fill the second portion of the recess (141 – Element 221 of 220 fills the recess 141).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the molding layer structure as taught by Yim into Shim, Lin, and Takahashi.
An ordinary artisan would have been motivated to use the known technique of Yim in the manner set forth above to produce the predictable results as stated above in claim 7.
Regarding claim 14, Shim as modified by Lin, Takahashi, and Chen, teaches claim 11 from which claim 14 depends. Shim, Lin, Takahashi, and Chen do not expressly disclose the limitations of claim 14.
However, in an analogous art, Lin teaches
the heat transfer material layer (262).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the heat transfer layer structure as taught by Lin into Shim, Lin, Takahashi, and Chen.
An ordinary artisan would have been motivated to use the known technique of Lin in the manner set forth above to produce the predictable results as stated above in claim 1.
Shim, Lin, Takahashi, and Chen do not expressly disclose the other limitations of claim 7.
However, in an analogous art, Yim teaches
wherein
the first molding layer (120 – Fig. 1 – [0029] – “semiconductor chip 120”)
includes:
a lower molding layer (140) configured to surround the sidewall of the first semiconductor chip (100); and
an upper molding layer (221 – Fig. 2 – [0038] – “first portion 221 of the insulating filler 220 may fill a gap between side walls of the conductive connectors 210 and an inner wall of the first molding layer 140 provided by the through holes 141 of the first molding layer 140”) configured to surround a
sidewall of the heat transfer material layer.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the molding layer structure as taught by Yim into Shim, Lin, Takahashi, and Chen.
An ordinary artisan would have been motivated to use the known technique of Yim in the manner set forth above to produce the predictable results as stated above in claim 7.
Conclusion
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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