DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 07/02/2026 have been fully considered but they are not persuasive.
Regarding claim 14, the applicants state that “Lofthouse … does not disclose current reconstruction error and the adjusting that error dynamically in real-time so that the error between the output voltage and the device current is minimized” on page 15. In the Office Action dated 04/03/2026, pages 7-8, the examiner cited elements and functions of Lofthouse as teaching this, particularly, Figs 1, 5A and paragraphs [0022], [0042]. The examiner respectfully request that the applicants directly address these cited elements and functions as to why the applicants believe they do not teach or suggest the claimed limitations.
Regarding claim 15-19, the applicants state that “Lofthouse contains no such [adaptive feedback] mechanism” on page 15. The adaptive feedback mechanism has not been expressly claimed. As such, the argument is moot.
Response to Amendment
Applicants’ Amendment filed on 07/02/2026 regarding claims 1-20 is fully considered. Of the above claims, claims 1-6, 14 and 20 have been amended.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 14-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lofthouse et al. (US 2021/0318368 A1).
Regarding claim 14, Lofthouse et al. teach a method for adaptive compensation for a current sensor (an accurate measurement of the resistance value of the sense resistor allows compensation for parasitic resistance; [0004]; the ADC 111 supplies the digital value of the sensed voltage to microcontroller 115, which determines whether the measured voltage corresponds to a current indicative of a safe power limit; power sourcing equipment PSE; [0022]; FIG. 1), comprising:
determining, by the current sensor, an output voltage based on a device current flowing through a power converter, the output voltage being representative of a measurement of the device current (when switch 514 is closed, differential amplifier 509 measures current from current source 501 or current source 503 flowing through Rsense 103; FIG. 5A; the voltage Vout is representative of current through sense resistor Rsense 103 and parasitic resistances Rp4 and Rp5);
determining, by the current sensor, an error of the output voltage as compared to the device current, the error caused by a voltage across a parasitic resistance existing in the power converter, the error corresponding to a current sensing error induced by the voltage across the parasitic resistance (resistances R 516, 518; ADC 511; MICROCONTROLLER; NVM; SRAM; switches 510 and 512; FIG. 5A; error of Vout caused by parasitic resistances Rp1, Rp2, Rp3, Rp4, Rp5 and Rp6; [0043]-[0053]); and
adjusting, by the current sensor, the error dynamically in real-time (the embodiment described by Figs 5A and 5B can be used operationally to periodically measure Rsense and account for changes in Rsense over time; [0058]; operationally and periodically suggest dynamically and in real-time).
Further regarding claim 14, the embodiment of Figs 5A and 5B of Lofthouse et al. does not teach the error between the output voltage and the device current is minimized.
Further regarding claim 14, another embodiment of Lofthouse et al. teaches or suggests the error between the output voltage and the device current is minimized (the parasitic value is saved and compensated for in future measurements; [0026]; the MICROCONTROLLER compensates for the measured and saved parasitic resistance effectively minimizing the error or changes) for the purpose of improving the accuracy of measurements.
Regarding claim 15, Lofthouse et al. teach determining, by the current sensor, a polarity of the output voltage, wherein the error is adjusted based on the polarity of the output voltage (the polarity of Vout at node 524 is determined by the difference of Vs+ and Vs-; converted to digital form by ADC 511 and input to the MICROCONTROLLER; saved parasitic resistance is compensated for based on Vout measurement including the polarity; FIG. 5A).
Regarding claim 16, Lofthouse et al. teach wherein adjusting the error further comprises:
generating an adjustable compensation coefficient (the parasitic value is saved and compensated for in future measurements; [0026]; the value used by the MICROCONTROLLER to compensate for the measured and saved parasitic resistance is the adjustable compensation coefficient); and
modifying the adjustable compensation coefficient based on the polarity of the output voltage (the source injection measurements can be repeated during operation to ensure that accurate resistance values are maintained to compensate for, e.g., temperature changes or other resistance drift; [0042]).
Regarding claim 17, Lofthouse et al. teach wherein modifying the adjustable compensation coefficient based on the polarity comprises increasing the adjustable compensation coefficient in response to the polarity being determined to be a positive value at an off-time of the power converter, the polarity being determined to be the positive value corresponding to a case of under-compensation of the output voltage as compared to the device current (the source injection measurements can be repeated during operation to ensure that accurate resistance values are maintained to compensate for, e.g., temperature changes or other resistance drift; [0042]; in a time of the PSE when the switch 514 is open, Vout1=VREF‒100(I1x(Rp4+Rsense+Rp5)+Vos); [0043]-[0053]; when under-compensated, Vout1 is positive).
Regarding claim 18, Lofthouse et al. teach wherein modifying the adjustable compensation coefficient based on the polarity comprises decreasing the adjustable compensation coefficient in response to the polarity being determined to be a negative value at an off-time of the power converter, the polarity being determined to be the positive value corresponding to a case of over-compensation of the output voltage as compared to the device current (the source injection measurements can be repeated during operation to ensure that accurate resistance values are maintained to compensate for, e.g., temperature changes or other resistance drift; [0042]; in a time of the PSE when the switch 514 is open, Vout1=VREF‒100(I1x(Rp4+Rsense+Rp5)+Vos); [0043]-[0053]; when under-compensated, Vout1 is positive).
Regarding claim 19, Lofthouse et al. teach wherein modifying the adjustable compensation coefficient based on the polarity comprises increasing the adjustable compensation coefficient in response to the polarity being determined to be a positive value at an off-time of the power converter and a positive value at an on-time of the power converter, the polarity being determined to be the positive value at the off-time and the on-time corresponding to a case of under-compensation of the output voltage as compared to the device current (in a time of the PSE when the switch 514 is open and in a time of the PSE when the switch 514 is closed; FIG. 5A; Vout1=VREF‒100(I1x(Rp4+Rsense+Rp5)+Vos); [0043]-[0053]; when under-compensated, Vout1 is positive).
Allowable Subject Matter
Claims 1-13 are allowed.
Claim 20 is objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
The primary reason for allowance of claim(s) 1-13 is the inclusion of “a sensing circuit configured to generate an output voltage based on a voltage across a parasitic inductance induced by a device current flowing through the power converter, the output voltage being representative of a measurement of the device current” and “adjust an error of the output voltage as compared to the device current, the error caused by a voltage across a parasitic resistance existing in the power converter, the error corresponding to a current sensing error induced by the voltage across the parasitic resistance”. These limitations, as they are claimed in the combination, have not been found, taught or suggested by the prior art of record, making claim(s) 1-13 allowable over the prior art.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for indicating allowable subject matter of claim(s) 20 is the inclusion of “a sensing circuit configured to generate the output voltage based on a voltage across a parasitic inductance” and “a compensation circuit electrically coupled to the sensing circuit and configured to determine and adjust the error, the compensation circuit comprising a compensation resistor and a processor”. These limitations, as they are claimed in the combination, have not been found, taught or suggested by the prior art of record, making claim(s) 20 allowable over the prior art.
Conclusion
Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENDRICK X LIU whose telephone number is (571)270-3798. The examiner can normally be reached MWFSa 10am-8pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Douglas X Rodriguez can be reached at (571) 431-0716. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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3 September 2026
/KENDRICK X LIU/Examiner, Art Unit 2853
/DOUGLAS X RODRIGUEZ/Supervisory Patent Examiner, Art Unit 2853
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