DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation of “the current sensor is electrically coupled between a first switch and a second switch of the power converter” (claim 13) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 1 is objected to because of the following informalities:
Regarding claim 1, the recitation of “a power converter” in line 3 refers to a previously recited limitation. Therefore, claim 1 at line 3 should recite “the power converter”
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 3-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lofthouse et al. (US 2021/0318368 A1).
Regarding claim 1, Lofthouse et al. teach a current sensor for a power converter (the ADC 111 supplies the digital value of the sensed voltage to microcontroller 115, which determines whether the measured voltage corresponds to a current indicative of a safe power limit; power sourcing equipment PSE; [0022]; FIG. 1), comprising:
a sensing circuit configured to generate an output voltage based on a device current flowing through a power converter, the output voltage being representative of a measurement of the device current (when switch 514 is closed, differential amplifier 509 measures current from current source 501 or current source 503 flowing through Rsense 103; FIG. 5A); and
a compensation circuit electrically coupled to the sensing circuit and comprising a compensation resistor and a processor (resistances R 516, 518; ADC 511; MICROCONTROLLER; NVM; SRAM; switches 510 and 512; FIG. 5A; the parasitic resistance values Rpn’s can be used during operation of the PSE to more accurately determine power being supplied to the load; the source injection measurements can be repeated during operation to ensure that accurate resistance values are maintained to compensate for, e.g., temperature changes or other resistance drift; [0042]), the compensation circuit configured to:
receive the output voltage (the input of ADC 511 receives Vout at node 524); and
adjust an error of the output voltage as compared to the device current, the error caused by a parasitic resistance existing in the power converter (the parasitic value is saved and compensated for in future measurements; [0026]).
Regarding claim 3, Lofthouse et al. teach wherein, to adjust the error, the compensation circuit is further configured to:
determine a polarity of the output voltage (the polarity of Vout at node 524 is determined by the difference of Vs+ and Vs-; converted to digital form by ADC 511 and input to the MICROCONTROLLER; FIG. 5A); and
dynamically adjust the error based on the polarity of the output voltage (saved parasitic resistance is compensated for based on Vout measurement including the polarity; FIG. 5A).
Regarding claim 4, Lofthouse et al. teach wherein, to dynamically adjust the error based on the polarity of the output voltage, the compensation circuit is further configured to:
generate an adjustable compensation coefficient (the parasitic value is saved and compensated for in future measurements; [0026]; the value used by the MICROCONTROLLER to compensate for the measured and saved parasitic resistance is the adjustable compensation coefficient); and
modify the adjustable compensation coefficient based on the polarity of the output voltage (the source injection measurements can be repeated during operation to ensure that accurate resistance values are maintained to compensate for, e.g., temperature changes or other resistance drift; [0042]).
Regarding claim 5, Lofthouse et al. teach wherein the compensation resistor in combination with the adjustable compensation coefficient substantially cancels the parasitic resistance (resistances R 516 and 518 together with other elements in the circuit of FIG. 5A substantially cancels the measured parasitic resistance).
Regarding claim 6, Lofthouse et al. teach wherein, to modify the adjustable compensation coefficient based on the polarity, the compensation circuit is further configured to increase the adjustable compensation coefficient in response to the polarity being determined to be a positive value at an off-time of the power converter, the polarity being determined to be the positive value corresponding to a case of under-compensation of the output voltage as compared to the device current (the source injection measurements can be repeated during operation to ensure that accurate resistance values are maintained to compensate for, e.g., temperature changes or other resistance drift; [0042]; in a time of the PSE when the switch 514 is open, Vout1=VREF‒100(I1x(Rp4+Rsense+Rp5)+Vos); [0043]-[0053]; when under-compensated, Vout1 is positive).
Regarding claim 7, Lofthouse et al. teach wherein, to modify the adjustable compensation coefficient based on the polarity, the compensation circuit is further configured to decrease the adjustable compensation coefficient in response to the polarity being determined to be a negative value at an off-time of the power converter, the polarity being determined to be the positive value corresponding to a case of over-compensation of the output voltage as compared to the device current (the source injection measurements can be repeated during operation to ensure that accurate resistance values are maintained to compensate for, e.g., temperature changes or other resistance drift; [0042]; in a time of the PSE when the switch 514 is open, Vout1=VREF‒100(I1x(Rp4+Rsense+Rp5)+Vos); [0043]-[0053]; when under-compensated, Vout1 is positive).
Regarding claim 8, Lofthouse et al. teach wherein the processor is configured to generate and modify the adjustable compensation coefficient based on the polarity of the output voltage (the source injection measurements can be repeated during operation to ensure that accurate resistance values are maintained to compensate for, e.g., temperature changes or other resistance drift; [0042]; in a time of the PSE when the switch 514 is open, Vout1=VREF‒100(I1x(Rp4+Rsense+Rp5)+Vos); [0043]-[0053]; when under-compensated or over-compensated, the value to compensate for the parasitic resistance is modified).
Regarding claim 9, Lofthouse et al. teach wherein the polarity of the output voltage is determined at an off-time of the power converter (in a time of the PSE when the switch 514 is open; FIG. 5A).
Regarding claim 10, Lofthouse et al. teach wherein the polarity of the output voltage is determined at both an off-time and an on-time of the power converter (in a time of the PSE when the switch 514 is open and in a time of the PSE when the switch 514 is closed; FIG. 5A).
Regarding claim 11, Lofthouse et al. teach wherein the error is dynamically adjusted based on a closed-loop control algorithm (the source injection measurements can be repeated during operation to ensure that accurate resistance values are maintained to compensate for, e.g., temperature changes or other resistance drift; [0042]; Figs 5A-5B).
Regarding claim 12, Lofthouse et al. teach wherein the current sensor is implemented in a printed circuit board PCB (PSE board; [0025]).
Regarding claim 13, Lofthouse et al. teach wherein the current sensor is electrically coupled between a first switch and a second switch of the power converter (amplifier 509 is coupled between switch 510 and switch 512; FIG. 5A).
Regarding claim 14, Lofthouse et al. teach a method for adaptive compensation for a current sensor (the ADC 111 supplies the digital value of the sensed voltage to microcontroller 115, which determines whether the measured voltage corresponds to a current indicative of a safe power limit; power sourcing equipment PSE; [0022]; FIG. 1), comprising:
determining, by the current sensor, an output voltage based on a device current flowing through a power converter, the output voltage being representative of a measurement of the device current (when switch 514 is closed, differential amplifier 509 measures current from current source 501 or current source 503 flowing through Rsense 103; FIG. 5A);
determining, by the current sensor, an error of the output voltage as compared to the device current, the error caused by a parasitic resistance existing in the power converter (resistances R 516, 518; ADC 511; MICROCONTROLLER; NVM; SRAM; switches 510 and 512; FIG. 5A; the parasitic resistance values Rpn’s can be used during operation of the PSE to more accurately determine power being supplied to the load; the source injection measurements can be repeated during operation to ensure that accurate resistance values are maintained to compensate for, e.g., temperature changes or other resistance drift; [0042]); and
adjusting, by the current sensor, the error dynamically in real-time so that the error between the output voltage and the device current is minimized (the source injection measurements can be repeated during operation to ensure that accurate resistance values are maintained to compensate for, e.g., temperature changes or other resistance drift; [0042]).
Regarding claim 15, Lofthouse et al. teach determining, by the current sensor, a polarity of the output voltage, wherein the error is adjusted based on the polarity of the output voltage (the polarity of Vout at node 524 is determined by the difference of Vs+ and Vs-; converted to digital form by ADC 511 and input to the MICROCONTROLLER; saved parasitic resistance is compensated for based on Vout measurement including the polarity; FIG. 5A).
Regarding claim 16, Lofthouse et al. teach wherein adjusting the error further comprises:
generating an adjustable compensation coefficient (the parasitic value is saved and compensated for in future measurements; [0026]; the value used by the MICROCONTROLLER to compensate for the measured and saved parasitic resistance is the adjustable compensation coefficient); and
modifying the adjustable compensation coefficient based on the polarity of the output voltage (the source injection measurements can be repeated during operation to ensure that accurate resistance values are maintained to compensate for, e.g., temperature changes or other resistance drift; [0042]).
Regarding claim 17, Lofthouse et al. teach wherein modifying the adjustable compensation coefficient based on the polarity comprises increasing the adjustable compensation coefficient in response to the polarity being determined to be a positive value at an off-time of the power converter, the polarity being determined to be the positive value corresponding to a case of under-compensation of the output voltage as compared to the device current (the source injection measurements can be repeated during operation to ensure that accurate resistance values are maintained to compensate for, e.g., temperature changes or other resistance drift; [0042]; in a time of the PSE when the switch 514 is open, Vout1=VREF‒100(I1x(Rp4+Rsense+Rp5)+Vos); [0043]-[0053]; when under-compensated, Vout1 is positive).
Regarding claim 18, Lofthouse et al. teach wherein modifying the adjustable compensation coefficient based on the polarity comprises decreasing the adjustable compensation coefficient in response to the polarity being determined to be a negative value at an off-time of the power converter, the polarity being determined to be the positive value corresponding to a case of over-compensation of the output voltage as compared to the device current (the source injection measurements can be repeated during operation to ensure that accurate resistance values are maintained to compensate for, e.g., temperature changes or other resistance drift; [0042]; in a time of the PSE when the switch 514 is open, Vout1=VREF‒100(I1x(Rp4+Rsense+Rp5)+Vos); [0043]-[0053]; when under-compensated, Vout1 is positive).
Regarding claim 19, Lofthouse et al. teach wherein modifying the adjustable compensation coefficient based on the polarity comprises increasing the adjustable compensation coefficient in response to the polarity being determined to be a positive value at an off-time of the power converter and a positive value at an on-time of the power converter, the polarity being determined to be the positive value at the off-time and the on-time corresponding to a case of under-compensation of the output voltage as compared to the device current (in a time of the PSE when the switch 514 is open and in a time of the PSE when the switch 514 is closed; FIG. 5A; Vout1=VREF‒100(I1x(Rp4+Rsense+Rp5)+Vos); [0043]-[0053]; when under-compensated, Vout1 is positive).
Regarding claim 20, Lofthouse et al. teach wherein the current sensor comprises:
a sensing circuit configured to generate the output voltage (when switch 514 is closed, differential amplifier 509 measures current from current source 501 or current source 503 flowing through Rsense 103; FIG. 5A); and
a compensation circuit electrically coupled to the sensing circuit and configured to determine and adjust the error, the compensation circuit comprising a compensation resistor and a processor (resistances R 516, 518; ADC 511; MICROCONTROLLER; NVM; SRAM; switches 510 and 512; FIG. 5A; the parasitic resistance values Rpn’s can be used during operation of the PSE to more accurately determine power being supplied to the load; the source injection measurements can be repeated during operation to ensure that accurate resistance values are maintained to compensate for, e.g., temperature changes or other resistance drift; [0042]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lofthouse et al. (US 2021/0318368 A1) in view of Nelatury (US 11,486,905 B1).
Regarding claim 2, Lofthouse et al. do not teach wherein:
the sensing circuit is an integrator circuit; and
the sensing circuit is configured to generate the output voltage based on integrating a voltage presented across a parasitic inductance existing in the power converter over a period of time.
Further regarding claim 2, Nelatury teaches wherein:
a sensing circuit is an integrator circuit (an integrator for use with current sensors; column 6, lines 25-61; FIG. 2); and
the sensing circuit is configured to generate the output voltage based on integrating a voltage over a period of time (the first negative swing at the output Vout 15 and second negative swing of Vout 15; column 5, lines 25-60; when a signal from a current sensor as a Rogowski coil is connected at Vn 2 the integrator thus constructed provides a Vout 15 from the op-amp a signal which may be read by a meter, and which signal provides an accurate measurement of the current with reduced drift and wide bandwidth; column 6, lines 33-51; the integrator being capable of integrating a voltage across a parasitic inductance at the input) for the purpose of providing a feedback loop capable of reducing drift and maintaining bandwidth.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein: the sensing circuit is an integrator circuit; and the sensing circuit is configured to generate the output voltage based on integrating a voltage presented across a parasitic inductance existing in the power converter over a period of time, as taught by Nelatury, into Lofthouse et al. for the purpose of providing a feedback loop capable of reducing drift and maintaining bandwidth.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENDRICK X LIU whose telephone number is (571)270-3798. The examiner can normally be reached MWFSa 10am-8pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Douglas X Rodriguez can be reached at (571) 431-0716. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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31 March 2026
/KENDRICK X LIU/Examiner, Art Unit 2853
/DOUGLAS X RODRIGUEZ/Supervisory Patent Examiner, Art Unit 2853