DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/21/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21, 22, 23, 26-31, 34-39 are rejected under 35 U.S.C. 103 as being unpatentable over Li (US 20190324683) and further in view of Park (US 20140223083) and further in view of Klein (US 20200218465)
Claim 21. Li discloses A method (eg., 0004 - initiated defrag operation), comprising:
receiving, at a memory controller, a command to defragment at least a portion of a NAND- based memory device (eg., 0031, 0050 - host 110 issues a defrag operation for BAND 3 to the host-managed storage device 120; 0022 - NVM-based storage device 120 );
analyzing, by the memory controller, the at least the portion of the NAND-based memory device to determine an amount of degraded performance due to invalid data by determining an amount and invalid data (eg., 0004 - host-initiated defrag operation selects the group(s)/band(s) to be defragmented based on which ones have the greatest number of IUs that contain stale/invalid data.; 0050 Fig. 4B - defrag operation for those bands meeting a threshold number of invalid Ills, i.e., having reached a level of invalidity that requires defragmentation for the host-managed device 120 to perform efficiently; 0024 Fig. 1 – controller 124; 0022 Fig. 1 NVM storage 122);
compacting, by the memory controller, valid data in the at least the portion of the NAND- based memory device (eg., 0044 - relocating valid data from the Source band to the Target band); and
returning a status of defragmentation to a host device (eg., 0044 - controller 124 will send a completion message to the host 110).
Li does not disclose, but Park discloses
wherein compacting the valid data comprises moving data for the defragmentation of the at least the portion of the NAND-based memory device by maintaining related data in contiguous logical block address (LBA) blocks (eg., [0109] Referring to FIG. 9E, the memory controller 200 may allocate a new block to move file fragments A6 and A7 in the fourth zone Z3. ; 0112 - file fragments in the same zone may be sequentially rearranged by changing mapping information using an LBA (logical block addressing) command; 0119 - The LBA move (3, 0, 3) may be to move three continuous file fragments from a logical address 3 as a start address to a logical address 0 as a destination address);
of valid (eg., 0039 - every time data is updated, pointer(s) corresponding to one or more invalid pages are added to the mapping table 400b such that the controller 112 can keep track of both valid and invalid pages corresponding to a logical address.)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the defrag operations as disclosed by Li, and Park, providing the benefit of Periodic defragmentation may help maintain the optimal performance of memory systems and constituent data media by reducing the file system overhead and data search time caused by excessive fragmentation (see Park, 0006).
Li in view of Park does not disclose, but Klein discloses
as specified by a logical block address (LBA) range in the command; locating, by the memory controller, records associated with the LBA range within a logical-to-physical (L2P) table of the memory controller to determine valid and invalid data without exchanging underlying stored data with a host device (eg., Fig. 3, 0033-0034; mapping table that maps each logical address to pages in the SSD 110 … FIG. 4B shows a mapping table 400b that maps each logical address to valid and invalid pages; 0034 - [0034] At 310, the controller 112 maps a logical address to a list of pointers (physical addresses). Each of the list of pointers corresponds to a respective one of valid and invalid pages… etadata 400a for a particular block, in addition to providing a flag identifier with respect to each page that indicates whether that page is valid, invalid);
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the defrag operations as disclosed by Li, and Park, with Klein providing the benefit of SSD controller updates a mapping table such that the pages associated with the logical address may be determined to be invalid and ready to be garbage-collected (see Klein, 0013) In addition to or alternatively to using the block metadata 400a to keep track of invalid pages and corresponding logical addresses, the mapping table 400b can be used (0035).
Claim 22. Li discloses wherein the at least the portion of the NAND-based memory device comprises a logical block address (LBA) range (eg., 0048 Fig. 4A - specified LBAs so that the storage device 120 and controller 124 can internally maintain a defrag).
Claim 23. Li discloses wherein the LBA range is indicated in the command (eg., 0048 - a host issues a request to a host-managed storage device 120, such as an SSD, to perform a Host Write command, specifying one or more LBAs, Physical Address and Length, or a Host Trim, specifying one or more LBAs and Length.).
Claim 26. Li discloses wherein the NAND-based memory device comprises a universal flash storage (UFS) device (eg., 0028 - NAND flash memory).
Claim 27. Li discloses wherein the memory controller utilizes a universal flash storage (UFS) interface (eg., 0025 - I/O interface 113, I/O interface 123 and link 130 may be arranged to operate according to one or more communication protocols and/or memory or storage access technologies.)
Claim 28. Li discloses wherein analyzing the at least the portion of the NAND- based memory device comprises determining an amount of performance degradation due to invalid data (eg., [0004] The host also maintains an invalidity table to track the invalidity of each group/band in terms of IU granularity, i.e., how many IUs in a given group/band contain stale or otherwise invalid data. The host uses the invalidity table to determine when to initiate a defragmentation (defrag) operation to free up NAND space).
Claim 29. Li discloses Non-transitory, computer-readable medium having stored thereon instructions, that when executed by a processor, are configured to cause the processor to (eg., [0012] For host-managed SSDs; 0004 - initiated defrag operation), comprising:
receive, at a memory controller from a host processor, a command to defragment at least a portion of a NAND-based memory device (eg., 0031, 0050 - host 110 issues a defrag operation for BAND 3 to the host-managed storage device 120; 0022 - NVM-based storage device 120 );
analyze, by the memory controller, the at least the portion of the NAND-based memory device to determine an amount of degraded performance due to invalid data by determining an amount of valid and invalid data; (eg., 0004 - host-initiated defrag operation selects the group(s)/band(s) to be defragmented based on which ones have the greatest number of IUs that contain stale/invalid data.; 0050 Fig. 4B - defrag operation for those bands meeting a threshold number of invalid Ills, i.e., having reached a level of invalidity that requires defragmentation for the host-managed device 120 to perform efficiently; 0024 Fig. 1 – controller 124; 0022 Fig. 1 NVM storage 122);
compact, by the memory controller, valid data in the at least the portion of the NAND- based memory device (eg., 0044 - relocating valid data from the Source band to the Target band); and
return a status of defragmentation to the host processor (eg., 0044 - controller 124 will send a completion message to the host 110).
Li does not disclose, but Park discloses
wherein compacting the valid data comprises moving data for the defragmentation of the at least the portion of the NAND-based memory device by maintaining related data in contiguous LBA blocks (eg., [0109] Referring to FIG. 9E, the memory controller 200 may allocate a new block to move file fragments A6 and A7 in the fourth zone Z3. ; 0112 - file fragments in the same zone may be sequentially rearranged by changing mapping information using an LBA (logical block addressing) command; 0119 - The LBA move (3, 0, 3) may be to move three continuous file fragments from a logical address 3 as a start address to a logical address 0 as a destination address);
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the defrag operations as disclosed by Li, and Park, providing the benefit of Periodic defragmentation may help maintain the optimal performance of memory systems and constituent data media by reducing the file system overhead and data search time caused by excessive fragmentation (see Park, 0006).
Li in view of Park does not disclose, but Klein discloses
as specified by a logical block address (LBA) range in the command; locate, by the memory controller, records associated with the LBA range within a logical-to-physical (L2P) table of the memory controller to determine valid and invalid data without exchanging underlying stored data with a host processor (eg., Fig. 3, 0033-0034; mapping table that maps each logical address to pages in the SSD 110 … FIG. 4B shows a mapping table 400b that maps each logical address to valid and invalid pages; 0034 - [0034] At 310, the controller 112 maps a logical address to a list of pointers (physical addresses). Each of the list of pointers corresponds to a respective one of valid and invalid pages… etadata 400a for a particular block, in addition to providing a flag identifier with respect to each page that indicates whether that page is valid, invalid);
of valid (eg., 0039 - every time data is updated, pointer(s) corresponding to one or more invalid pages are added to the mapping table 400b such that the controller 112 can keep track of both valid and invalid pages corresponding to a logical address.)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the defrag operations as disclosed by Li, and Park, with Klein providing the benefit of SSD controller updates a mapping table such that the pages associated with the logical address may be determined to be invalid and ready to be garbage-collected (see Klein, 0013) In addition to or alternatively to using the block metadata 400a to keep track of invalid pages and corresponding logical addresses, the mapping table 400b can be used (0035).
Claim 30 is rejected for reasons similar to Claim 22 above.
Claim 31 is rejected for reasons similar to Claim 23 above.
Claim 34 is rejected for reasons similar to Claim 26 above.
Claim 35 is rejected for reasons similar to Claim 27 above.
Claim 36 is rejected for reasons similar to Claim 28 above.
Claim 37. Li discloses A system, comprising: flash memory device configured to store data of a host device; and a memory controller comprising an interface with the host device, wherein the memory controller is configured to (eg., 0021 - FIG. 1, system 100 includes a host CPU 110 coupled to a host-managed storage device 120), comprising:
receive a command via the interface to defragment at least a portion of the flash memory device (eg., 0031, 0050 - host 110 issues a defrag operation for BAND 3 to the host-managed storage device 120; 0022 - NVM-based storage device 120 );
analyze the at least the portion of the flash memory device to determine an amount of degraded performance due to invalid data by determining an amount of and invalid data (eg., 0004 - host-initiated defrag operation selects the group(s)/band(s) to be defragmented based on which ones have the greatest number of IUs that contain stale/invalid data.; 0050 Fig. 4B - defrag operation for those bands meeting a threshold number of invalid Ills, i.e., having reached a level of invalidity that requires defragmentation for the host-managed device 120 to perform efficiently; 0024 Fig. 1 – controller 124; 0022 Fig. 1 NVM storage 122);
compact valid data in the at least the portion of the flash memory device (eg., 0044 - relocating valid data from the Source band to the Target band); and
return a status of defragmentation to the host device (eg., 0044 - controller 124 will send a completion message to the host 110).
Li does not disclose, but Park discloses
wherein compacting the valid data comprises moving data for the defragmentation of the at least the portion of the NAND-based memory device by maintaining related data in contiguous LBA blocks (eg., [0109] Referring to FIG. 9E, the memory controller 200 may allocate a new block to move file fragments A6 and A7 in the fourth zone Z3. ; 0112 - file fragments in the same zone may be sequentially rearranged by changing mapping information using an LBA (logical block addressing) command; 0119 - The LBA move (3, 0, 3) may be to move three continuous file fragments from a logical address 3 as a start address to a logical address 0 as a destination address);
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the defrag operations as disclosed by Li and Park, providing the benefit of Periodic defragmentation may help maintain the optimal performance of memory systems and constituent data media by reducing the file system overhead and data search time caused by excessive fragmentation (see Park, 0006).
Li in view of Park does not disclose, but Klein discloses
as specified by a logical block address (LBA) range in the command; locate records associated with the LBA range within a logical-to-physical (L2P) table of the memory controller to determine valid and invalid data without exchanging underlying stored data with a host device (eg., Fig. 3, 0033-0034; mapping table that maps each logical address to pages in the SSD 110 … FIG. 4B shows a mapping table 400b that maps each logical address to valid and invalid pages; 0034 - [0034] At 310, the controller 112 maps a logical address to a list of pointers (physical addresses). Each of the list of pointers corresponds to a respective one of valid and invalid pages… etadata 400a for a particular block, in addition to providing a flag identifier with respect to each page that indicates whether that page is valid, invalid);
of valid (eg., 0039 - every time data is updated, pointer(s) corresponding to one or more invalid pages are added to the mapping table 400b such that the controller 112 can keep track of both valid and invalid pages corresponding to a logical address.)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the defrag operations as disclosed by Li and Park, with Klein providing the benefit of SSD controller updates a mapping table such that the pages associated with the logical address may be determined to be invalid and ready to be garbage-collected (see Klein, 0013) In addition to or alternatively to using the block metadata 400a to keep track of invalid pages and corresponding logical addresses, the mapping table 400b can be used (0035).
Claim 38. Li discloses comprising a processor that acts as the host device (eg., 0021 – Fig. 1 - a host CPU 110 ).
Claim 39. Li discloses wherein the flash memory device comprises a universal flash storage (UFS) device (eg., 0028 - NAND flash memory). and
the command comprises an LBA range indicating bounds of the at least the portion of the flash memory device (eg., 0004 - defrag operation selects the group(s)/band(s) to be defragmented based on which ones have the greatest number of IUs that contain stale/invalid data; 0048 Fig. 4A - specified LBAs so that the storage device 120 and controller 124 can internally maintain a defrag; 0029 - multiple contiguous LBAs, ; 0048 - Host Write command, specifying one or more LBAs, Physical Address and Length, or a Host Trim, specifying one or more LBAs and Length). .
Response to Arguments
Applicant's arguments filed 3/25/2026 (via RCE filed 4/21/2026) have been fully considered but they are not persuasive.
For claims 21, 29 and 37, Applicant argues that that the cited references do not disclose the amended limitations. The Office disagrees.
In the present OA, the updated combination of references render the amended limitations as obvious.
Specifically, Li in view of Park does not disclose, but Klein discloses
as specified by a logical block address (LBA) range in the command; locating, by the memory controller, records associated with the LBA range within a logical-to-physical (L2P) table of the memory controller to determine valid and invalid data without exchanging underlying stored data with a host device (eg., Fig. 3, 0033-0034; mapping table that maps each logical address to pages in the SSD 110 … FIG. 4B shows a mapping table 400b that maps each logical address to valid and invalid pages; 0034 - [0034] At 310, the controller 112 maps a logical address to a list of pointers (physical addresses). Each of the list of pointers corresponds to a respective one of valid and invalid pages… etadata 400a for a particular block, in addition to providing a flag identifier with respect to each page that indicates whether that page is valid, invalid);
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the defrag operations as disclosed by Li, and Park, with Klein providing the benefit of SSD controller updates a mapping table such that the pages associated with the logical address may be determined to be invalid and ready to be garbage-collected (see Klein, 0013) In addition to or alternatively to using the block metadata 400a to keep track of invalid pages and corresponding logical addresses, the mapping table 400b can be used (0035).
Applicant’s arguments for dependent claims are based on their respective base independent claims 21, 29 and 37, which are addressed above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GAUTAM SAIN whose telephone number is (571)270-3555. The examiner can normally be reached M-F 9-5.
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/GAUTAM SAIN/Primary Examiner, Art Unit 2135
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