DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-10, 12-14, 16-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0132159 A1 (“Xiu”) in view of US 2021/0084315 A1 (“Chen”).
Regarding claim 1, Xiu discloses a method of decoding video data, the method comprising: determining that vector information for a current block of video data is to be coded using a merge with vector difference mode (e.g. see at least merge mode with motion vector difference (MMVD) flag and/or first control flag and/or second control flag, paragraphs [0077], [0118]-[0121]); decoding data indicative of a search process to be used for the merge with vector difference mode to determine a vector difference for the vector information, the data indicative of the search process comprising data indicating a multi-stage search process (e.g. see at least determining whether to enable decoder side motion vector refinement (DMVR) for the MMVD mode, e.g. based if signaled MMVD offset is larger than threshold, paragraphs [0112]-[0115]; thus, if DMVR is enabled for the MMVD, the search process involves DMVR based on bilateral-matching search involving integer search stage and fractional sample refinement stage, paragraphs [0083]-[0085]; if DMVR is not enabled for the MMVD mode, then the search process involves MMVD mode search to find and select the MVD offset based on rate-distortion optimization, see paragraph [0115]); selecting a merge candidate from a merge candidate list to determine a vector predictor for the vector information (e.g. see at least in the MMVD mode, the first two candidates in the merge list for regular merge mode are selected as the two base merge candidates for MMVD, paragraphs [0076]-[0080]); performing the search process to determine the vector difference (e.g. see at least forming the MVD based on the selected MVD offset and MVD direction, paragraph [0122], e.g. either using MMVD mode search or using DMVR for the MMVD, paragraphs [0112]-[0115]); applying the vector difference to the vector predictor to form a final vector (e.g. see at least applying the formed MVD to generate the motion vectors to the respective coding unit, paragraph [0123]); and forming a prediction block for the current block using the final vector (e.g. see at least reconstructs the respective coding unit by applying the formed MVD to generate the motion vectors to the respective coding unit, paragraph [0123], e.g. to produce prediction block as illustrated in Fig. 3).
Although Xiu discloses decoding data indicative of a search process to be used for the merge with vector difference mode to determine a vector difference for the vector information, the data indicative of the search process comprising data indicating a multi-stage search process, it is noted Xiu differs from the present invention in that it fails to particularly disclose whether the search process is a single-stage search process. Chen however, teaches whether the search process is a single-stage search process (e.g. see Fig. 6 illustrating to disable or conditionally invoke fractional search 622 depending on the check at step 621, paragraphs [0115]-[0119]).
Therefore, given the teachings as a whole, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the references of Xiu and Chen before him/her, to modify the Merge mode with motion vector differences of Xiu with the teachings of Chen in order to reduce computational complexity.
Regarding claim 3, Xiu further discloses wherein decoding the data indicative of the search process comprises decoding at least one of a sequence parameter set (SPS), a picture parameter set (PPS), a slice header, or a block header including the data indicative of the search process (e.g. see at least signaling at different coding levels, e.g., sequence-level, picture-level, and/or slice level, etc. paragraph [0105]).
Regarding claim 4, Xiu further discloses wherein decoding the data indicative of the search process comprises decoding the data indicative of the search process in response to determining that the merge with vector difference mode is enabled for the current block (e.g. see at least DMVR is only applied to the MMVD CUs when the signaled MMVD offset is larger than one threshold, paragraphs [0112]-[0115]).
Regarding claim 5, Xiu further discloses wherein determining that the merge with vector difference mode is enabled for the current block comprises coding data of a sequence parameter set (SPS) or a picture parameter set (PPS) indicating that the merge with vector difference mode is enabled for the current block (e.g. see at least merge mode with motion vector difference (MMVD) flag and/or first control flag and/or second control flag, paragraphs [0077], [0118]-[0121], and see signaling at different coding levels, e.g., sequence-level, picture-level, and/or slice level, etc. paragraph [0105]).
Regarding claim 6, Xiu further discloses wherein selecting the merge candidate comprises decoding a merge candidate index indicative of the merge candidate in the merge candidate list (e.g. see at least merge index, paragraphs [0076]-[0080]).
Regarding claim 7, Xiu further discloses wherein the data indicative of the search process comprises the data indicating that the search process is the multi-stage search process (e.g. see at least determining whether to enable decoder side motion vector refinement (DMVR) for the MMVD mode, e.g. based if signaled MMVD offset is larger than threshold, paragraphs [0112]-[0115]; thus, if DMVR is enabled for the MMVD, the search process involves DMVR based on bilateral-matching search involving integer search stage and fractional sample refinement stage, paragraphs [0083]-[0085]; if DMVR is not enabled for the MMVD mode, then the search process involves MMVD mode search to find and select the MVD offset based on rate-distortion optimization, see paragraph [0115]), and wherein performing the search process comprises performing a first search in an integer pixel domain and performing a second search in a fractional pixel domain (e.g. see at least integer sample search and fractional sample refinement, paragraphs [0081]-[0087]).
Regarding claim 8, Xiu further discloses wherein performing the first search comprises performing the first search as a first search phase, and wherein performing the second search comprises performing the second search as a second search phase following the first search phase and starting at a result of the first search phase (e.g. see at least the stage of integer sample search is followed by fractional sample refinement, paragraphs [0081]-[0087]).
Regarding claim 9, Xiu further discloses wherein performing the first search comprises testing a plurality of integer value offsets relative to the vector predictor (e.g. see at least the SAD of 21 integer sample positions (including the integer sample position corresponding to the initial MV) as indicated in Fig. 7 are checked, paragraphs [0081]-[0087]).
Regarding claim 10, Xiu further discloses wherein performing the search process comprises searching only potential vector differences that, when applied to the vector information, refer to a reference block for which all pixels needed for calculating a difference metric are available in a reference area (e.g. see at least DMVR search range is +/- 2-pel from initial MVs based on bilateral-matching search (e.g. see Fig. 6 based on SAD, paragraphs [0081]-[0083]) and see MVD offsets used by the MMVD mode can also cover such search range (e.g. see Table 3) based on more accurate and reliable RDO, as a result, within the small local region around the initial MVs, the MVD offset signaled by the MMVD should be more accurate than of the DMVR and DMVR may be disallowed for this case, paragraphs [0112]-[0115]).
Regarding claim 12, Xiu further discloses further comprising decoding the current block using the prediction block (e.g. see at least video decoder 30 using the prediction block as shown in Fig. 3).
Regarding claim 13, Xiu further discloses further comprising encoding the current block prior to decoding the current block (e.g. see at least video encoder 20 in Fig. 2 encoding video data to output encoded video bitstream in Fig. 2 that is received by video decoder 30 as shown in Fig. 3).
Regarding claim 19, Xiu further discloses further comprising a display configured to display decoded video data (e.g. see display device 34 in Fig. 1, paragraph [0031]).
Regarding claim 20, Xiu further discloses wherein the device comprises one or more of a camera, a computer, a mobile device, a broadcast receiver device, or a set-top box (e.g. see at least paragraph [0025]).
Regarding claim 21, although Xiu discloses wherein the multi-stage search process comprises searching only vector candidates having integer pixel precision in a first stage to select a selected integer precision block vector candidate and, after the first stage, performing a second stage to determine a fractional precision refinement to the selected integer precision block vector candidate (e.g. see at least integer sample search stage followed by fractional sample refinement stage, paragraphs [0081]-[0087]), it is noted Xiu differs from the present invention in that it fails to particularly disclose wherein the single-stage search process comprises searching vector candidates having either integer or fractional pixel precision. Chen however, teaches wherein the single-stage search process comprises searching vector candidates having either integer or fractional pixel precision (e.g. see integer sample offset search stage 610 in Fig. 6, paragraphs [0115]-[0119]). The motivation above in the rejection of claim 1 applies here.
Regarding claims 14, 16-18, 22, the claims recite analogous limitations to the claims above and are therefore rejected on the same premise.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xiu in view of Chen in further view of US 2025/0184476 A1 (“Jang”).
Regarding claim 11, although Xiu discloses the pixels needed for calculating the difference metric, it is noted Xiu differs from the present invention in that it fails to particularly disclose wherein the pixels needed for calculating the difference metric comprise at least one of pixels needed for performing interpolation pixels needed for performing template matching refinement. Jang however, teaches wherein the pixels needed for calculating the difference metric comprise at least one of pixels needed for performing interpolation or pixels needed for performing template matching refinement (e.g. see interpolation or template matching in Fig. 9, paragraphs [0141], [0151]).
Therefore, given the teachings as a whole, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the references of Xiu, Chen and Jang before him/her, to incorporate the teachings of Jang into the Merge mode with motion vector differences of Xiu as modified by Chen in order to provide an image encoding/decoding method and apparatus with improved encoding/decoding efficiency.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3-14 and 16-22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2024/0406436 A1, Kim et al., Method, apparatus, and recording medium for image encoding/decoding
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRANCIS G GEROLEO whose telephone number is (571)270-7206. The examiner can normally be reached M-F 7:00 am - 3:30 pm.
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/Francis Geroleo/Primary Examiner, Art Unit 3619
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