Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
CLAIM INTERPRETATION
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Such claim limitations are: “contention assessment module, processing suspension module” in claim 7.
The specification discloses corresponding structure and algorithms, including that: “the contention assessment module is a hardware-specific module … the processing suspension module is a hardware-specific module” (paragraphs [0014] and [0015]).
Because these claim limitations are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, they are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made
Claims 1-9 and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Fumey et al. (US 2020/0034130 A1, hereinafter Fumey) in view of Mars et al. (US 9,268,542 B1, hereinafter Mars).
Regarding claim 1, Fumey discloses
a method for managing software application tasks being performed in a multi-core processing system (Abstract: method for installing avionics software applications on a platform with a multi-core processor; paragraph [0018]: platform comprising a multi-core processor having a plurality of separate cores), the method comprising:
determining a criticality level of each task to be performed (paragraphs [0089]-[0091]: Each avionics software application 14 for example has a criticality level corresponding to a DAL level… Level DAL A is the highest criticality level, and level DAL D is the lowest criticality level, according to the following sequencing: DAL A>DAL B>DAL C>DAL D);
allocating each task to a respective processing core of a plurality of processing cores based on the determined criticality level (paragraphs [0092]-[0093] and [0107]-[0108]: specific cores are reserved based on criticality, e.g., prohibiting critical software applications of DAL A or DAL B on cores C2 and C3, and reserving them for lower criticality DAL C or DAL D applications).
Fumey further discloses managing contention by detecting contentions and gradually stopping the least critical applications on other cores to protect critical applications (paragraphs [0026], [0141]).
However, Fumey does not disclose assigning a contention threshold to at least one processing core; monitoring an amount of contention caused by the at least one processing core that has been assigned the contention threshold; and upon determining the amount of contention reaches the assigned contention threshold, suspending processing on that processing core.
Mars discloses assigning a contention threshold to at least one processing core; monitoring an amount of contention caused by the at least one processing core that has been assigned the contention threshold; and upon determining the amount of contention reaches the assigned contention threshold, suspending processing on that processing core (col. 1, lines 37-62: determining a degree of contention among the first software application and the second software application; col. 2, lines 5-10: halting execution of the second software application on the second core for a first response period of time if the determined degree of contention exceeds a determined contention threshold; col. 3, lines 10-36: halt execution of the second application on the second processing core… if the degree of contention exceeds a determined contention threshold). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the multi-core task allocation method of Fumey to include assigning a contention threshold to a core, monitoring the contention, and suspending processing on that core when the threshold is reached, as taught by Mars. The motivation would have been to provides a low-overhead run-time solution that minimizes cross-core interference due to contention for shared resources (Mars, col. 6, lines 50-53).
Regarding claim 2, Fumey does not disclose further comprising: after a time interval has elapsed, resuming processing on the at least one processing core that was previously suspended. Mars discloses further comprising: after a time interval has elapsed, resuming processing on the at least one processing core that was previously suspended (col. 2, lines 5-10: halting execution of the second software application on the second core for a first response period of time if the determined degree of contention exceeds a determined contention threshold; col. 3, lines 10-36: halt execution of the second application on the second processing core… if the degree of contention exceeds a determined contention threshold; claim 2: temporarily halting execution of the second software application for a period of time, and resuming execution of the second software application when the period of time is passed). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the time-interval resumption taught by Mars into the modified system of Fumey. The motivation would have been to provides a low-overhead run-time solution that minimizes cross-core interference due to contention for shared resources (Mars, col. 6, lines 50-53).
Regarding claim 3, Fumey discloses
wherein determining a criticality level of each task to be performed comprises determining a Design Assurance Level, DAL, of each task (paragraph [0090]: Each avionics software application 14 for example has a criticality level corresponding to a DAL level defined according to standard DO-178 revision B and following, or according to standard ARP4754. Level DAL A is the highest criticality level, and level DAL D is the lowest criticality level, according to the following sequencing: DAL A>DAL B>DAL C>DAL D).
Regarding claim 4, Fumey discloses
wherein each processing core is associated with a particular DAL and tasks are allocated to the respective processing core having the associated DAL (paragraphs [0107]-[0108] and FIG. 4: specific cores are reserved for specific DAL levels, such as the third core C2 and fourth core C3 being reserved for applications having a criticality level equal to DAL C or DAL D; paragraph [0133]: the installation plan then indicates the installation of the partition 1 with criticality level DAL A on the first core C0, partition 2 with criticality level DAL B on the second core C1 and partition 3 with criticality level DAL C on the third core C2).
Regarding claim 5, Fumey discloses
a plurality of processing cores having different, descending determined criticality levels (paragraphs [0123]-[0124]: describing partition 1 as DAL A, partition 2 as DAL B, partition 3 as DAL C, and partition 4 as DAL D, and assigning different margins based on these descending criticality levels).
However, Fumey does not disclose wherein assigning a contention threshold to at least one processing core comprises assigning a respective contention threshold to all but one of the plurality of processing cores, wherein the assigned contention thresholds are all different from one another and wherein the lower the assigned contention threshold the lower the determined criticality level of the tasks allocated to the respective processing core. Mars discloses wherein assigning a contention threshold to at least one processing core comprises assigning a respective contention threshold to all but one of the plurality of processing cores, wherein the assigned contention thresholds are all different from one another and wherein the lower the assigned contention threshold the lower the determined criticality level of the tasks allocated to the respective processing core (col. 11, line 64-col. 12, line 12: number of parameters of the shutter-burst contention detection approach may be adjusted or tuned. In various examples, the parameters may be tuned to meet QoS requirements of the application … the runtime engine may adjust or vary the threshold difference (or impact threshold) that it uses to determine whether contention is occurring; col. 15, line 55-col. 16, line 15: the system handles contention response differently based on sensitivity, and is more willing to sacrifice utilization to eliminate contention for more sensitive/critical applications, and will adjust parameters of the approaches discussed herein to achieve these goals). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to scale the variable, sensitivity-based contention thresholds of Mars across the descending criticality architecture of Fumey. By doing so, the system would assign different contention thresholds to the lower-criticality cores (all but the highest criticality core) such that the lower the criticality level of the core, the lower its assigned contention threshold. The motivation would have been to scale the contention response across multiple applications of varying importance, thereby ensuring that the utilization of the least critical applications is sacrificed first to reduce the cross-core interference penalty experienced by the most critical applications (Mars col. 15, line 55-col. 16, line 15).
Regarding claim 6, Fumey does not explicitly disclose wherein the contention thresholds are assigned based on the chain rule: thresholdA > thresholdB, > thresholdC > thresholdN where A, B, C, N represent cores in descending order of criticality.
Fumey discloses a multi-core architecture with cores assigned in descending order of criticality (e.g., DAL A > DAL B > DAL C > DAL D) (paragraphs [0040], [0070]).
Mars discloses dynamically adjusting contention thresholds based on the application’s sensitivity, specifically teaching that the system is more willing to sacrifice utilization for lower-priority applications to protect higher-priority ones (col. 15, line 55-col. 16, line 15: the system handles contention response differently based on sensitivity, and is more willing to sacrifice utilization to eliminate contention for more sensitive/critical applications, and will adjust parameters of the approaches discussed herein to achieve these goas). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to formulate the sensitivity-based thresholding of Mars applied to the DAL-based cores of Fumey as a descending chain rule (thresholdA > thresholdB, > thresholdC > thresholdN). Expressing this relationship as a chain rule is merely a formal logical representation of the proportional threshold assignment already rendered obvious. The motivation would have been to scale the contention response across multiple applications of varying importance, thereby ensuring that the utilization of the least critical applications is sacrificed first to reduce the cross-core interference penalty experienced by the most critical applications (Mars col. 15, line 55-col. 16, line 15).
Regarding claim 7, Fumey discloses
A multi-core processing system comprising:
a management core configured to manage the allocation of processing tasks in the system (paragraphs [0086]-[0088]: an installation module 16 executing on the platform that manages the installation and allocation of avionics software applications/tasks; Note: Under the Broadest Reasonable Interpretation, because the installation module 16 is software that must execute on hardware, the processing core of the multi-core platform that executes the installation module 16 constitutes the claimed “management core.” The claim does not require the management core to be a dedicated hardware component distinct from the plurality of processing cores, only that a core is configured to perform the recited management function);
a plurality of processing cores configured to execute instructions for performing processing tasks (paragraph [0018]: platform comprising a multi-core processor having a plurality of separate cores);
at least one shared resource, wherein the at least one shared resource is connected to each of the plurality of processing cores (paragraph [0019]: the platform 12 comprises a shared memory 22 … accessible by each core);
wherein the system is configured to determine a criticality level of each task to be performed (paragraphs [0089]-[0091]: Each avionics software application 14 for example has a criticality level corresponding to a DAL level… Level DAL A is the highest criticality level, and level DAL D is the lowest criticality level, according to the following sequencing: DAL A>DAL B>DAL C>DAL D);
allocate each task to a respective processing core of a plurality of processing cores based on the determined criticality level (paragraphs [0092]-[0093] and [0107]-[0108]: specific cores are reserved based on criticality, e.g., prohibiting critical software applications of DAL A or DAL B on cores C2 and C3, and reserving them for lower criticality DAL C or DAL D applications).
Fumey further discloses managing contention by detecting contentions and gradually stopping the least critical applications on other cores to protect critical applications (paragraphs [0026], [0141]).
However, Fumey does not disclose a contention assessment module configured to monitor an amount of contention in the system; a processing suspension module configured to cause suspension of processing on at least one of the processing cores; and wherein the system is configured to assign a contention threshold to at least one processing core; monitor the amount of contention caused by the at least one processing core that has been assigned the contention threshold; and upon determining the amount of contention reaches the assigned contention threshold, suspending processing on that processing core. Mars discloses a contention assessment module configured to monitor an amount of contention in the system (col. 7, lines 9-12, col. 9, lines 53-55: CAER M engine 102a may be a monitoring engine to collect performance data and detect contention); a processing suspension module configured to cause suspension of processing on at least one of the processing cores (col. 6, lines 44-49: the runtime engine may use an empirical method to detect when two or more applications are contending for shared resources (e.g., a last level cache), and may stagger, pause, or shutter execution of a less important application to permit a more important application to execute with less contention; col. 7, lines 13-16: The CAER engine 102b may be a contention-detection-and-reaction engine, and is associated with the second core 106, on which the second (non-latency-sensitive) application 112 is executing); and wherein the system is configured to assign a contention threshold to at least one processing core; monitor the amount of contention caused by the at least one processing core that has been assigned the contention threshold; and upon determining the amount of contention reaches the assigned contention threshold, suspending processing on that processing core (col. 1, lines 37-62: determining a degree of contention among the first software application and the second software application; col. 2, lines 5-10: halting execution of the second software application on the second core for a first response period of time if the determined degree of contention exceeds a determined contention threshold; col. 3, lines 10-36: halt execution of the second application on the second processing core… if the degree of contention exceeds a determined contention threshold). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the multi-core system of Fumey to include the contention assessment module, processing suspension module, and threshold-based suspension logic taught by Mars. The motivation would have been to provides a low-overhead run-time solution that minimizes cross-core interference due to contention for shared resources (Mars, col. 6, lines 50-53).
Regarding claim 8, Fumey does not disclose wherein the contention assessment module is a hardware-specific module. Mars discloses wherein the contention assessment module is a hardware-specific module (col. 7, lines 9-12, col. 9, lines 53-55: CAER M engine 102a may be a monitoring engine to collect performance data and detect contention; col. 9, lines 20-30: multicore processors can include, within or associated with each processing core… various hardware-performance monitors that can provide real-time micro-architectural information; col. 19, lines 1-12: Various implementations of the systems and techniques described here can be realized in digital electronic circuitry, integrated circuitry, specially designed ASICs (application specific integrated circuits), computer hardware, firmware, software, and/or combinations thereof). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the contention assessment module of Mars as a hardware-specific module (e.g., using digital electronic circuitry or an ASIC) that interfaces directly with the processor’s hardware-performance monitors. The motivation would have been to provides a low-overhead run-time solution that minimizes cross-core interference due to contention for shared resources (Mars, col. 6, lines 50-53).
Regarding claim 9, Fumey does not disclose wherein the processing suspension module is a hardware-specific module. Mars discloses wherein the processing suspension module is a hardware-specific module (col. 6, lines 44-49: the runtime engine may use an empirical method to detect when two or more applications are contending for shared resources (e.g., a last level cache), and may stagger, pause, or shutter execution of a less important application to permit a more important application to execute with less contention; col. 7, lines 13-16: The CAER engine 102b may be a contention-detection-and-reaction engine, and is associated with the second core 106, on which the second (non-latency-sensitive) application 112 is executing; col. 9, lines 20-30: multicore processors can include, within or associated with each processing core… various hardware-performance monitors that can provide real-time micro-architectural information; col. 19, lines 1-12: Various implementations of the systems and techniques described here can be realized in digital electronic circuitry, integrated circuitry, specially designed ASICs (application specific integrated circuits), computer hardware, firmware, software, and/or combinations thereof). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the processing suspension module of Mars as a hardware-specific module (e.g., using digital electronic circuitry or an ASIC). The motivation would have been to provides a low-overhead run-time solution that minimizes cross-core interference due to contention for shared resources (Mars, col. 6, lines 50-53).
Regarding claim 11, Fumey does not disclose wherein the multi-core processing system is further configured to resume processing on the processing core that was previously suspended after a time interval has elapsed. Mars discloses wherein the multi-core processing system is further configured to resume processing on the processing core that was previously suspended after a time interval has elapsed (col. 2, lines 5-10: halting execution of the second software application on the second core for a first response period of time if the determined degree of contention exceeds a determined contention threshold; col. 3, lines 10-36: halt execution of the second application on the second processing core… if the degree of contention exceeds a determined contention threshold; claim 2: temporarily halting execution of the second software application for a period of time, and resuming execution of the second software application when the period of time is passed). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the time-interval resumption taught by Mars into the modified system of Fumey. The motivation would have been to provides a low-overhead run-time solution that minimizes cross-core interference due to contention for shared resources (Mars, col. 6, lines 50-53).
Regarding claim 12, Fumey discloses
wherein determining a criticality level of each task to be performed comprises determining a Design Assurance Level, DAL, of each task (paragraph [0090]: Each avionics software application 14 for example has a criticality level corresponding to a DAL level defined according to standard DO-178 revision B and following, or according to standard ARP4754. Level DAL A is the highest criticality level, and level DAL D is the lowest criticality level, according to the following sequencing: DAL A>DAL B>DAL C>DAL D).
Regarding claim 13, Fumey discloses
wherein each processing core is associated with a particular DAL and tasks are allocated to the respective processing core having the associated DAL (paragraphs [0107]-[0108] and FIG. 4: specific cores are reserved for specific DAL levels, such as the third core C2 and fourth core C3 being reserved for applications having a criticality level equal to DAL C or DAL D; paragraph [0133]: the installation plan then indicates the installation of the partition 1 with criticality level DAL A on the first core C0, partition 2 with criticality level DAL B on the second core C1 and partition 3 with criticality level DAL C on the third core C2).
Regarding claim 14, Fumey discloses
a plurality of processing cores having different, descending determined criticality levels (paragraphs [0123]-[0124]: describing partition 1 as DAL A, partition 2 as DAL B, partition 3 as DAL C, and partition 4 as DAL D, and assigning different margins based on these descending criticality levels).
However, Fumey does not disclose wherein assigning a contention threshold to at least one processing core comprises assigning a respective contention threshold to all but one of the plurality of processing cores, wherein the assigned contention thresholds are all different from one another and wherein the lower the assigned contention threshold the lower the determined criticality level of the tasks allocated to the respective processing core. Mars discloses wherein assigning a contention threshold to at least one processing core comprises assigning a respective contention threshold to all but one of the plurality of processing cores, wherein the assigned contention thresholds are all different from one another and wherein the lower the assigned contention threshold the lower the determined criticality level of the tasks allocated to the respective processing core (col. 11, line 64-col. 12, line 12: number of parameters of the shutter-burst contention detection approach may be adjusted or tuned. In various examples, the parameters may be tuned to meet QoS requirements of the application … the runtime engine may adjust or vary the threshold difference (or impact threshold) that it uses to determine whether contention is occurring; col. 15, line 55-col. 16, line 15: the system handles contention response differently based on sensitivity, and is more willing to sacrifice utilization to eliminate contention for more sensitive/critical applications, and will adjust parameters of the approaches discussed herein to achieve these goals). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to scale the variable, sensitivity-based contention thresholds of Mars across the descending criticality architecture of Fumey. By doing so, the system would assign different contention thresholds to the lower-criticality cores (all but the highest criticality core) such that the lower the criticality level of the core, the lower its assigned contention threshold. The motivation would have been to scale the contention response across multiple applications of varying importance, thereby ensuring that the utilization of the least critical applications is sacrificed first to reduce the cross-core interference penalty experienced by the most critical applications (Mars col. 15, line 55-col. 16, line 15).
Regarding claim 15, Fumey does not explicitly disclose wherein the contention thresholds are assigned based on the chain rule: thresholdA > thresholdB, > thresholdC > thresholdN where A, B, C, N represent cores in descending order of criticality.
Fumey discloses a multi-core architecture with cores assigned in descending order of criticality (e.g., DAL A > DAL B > DAL C > DAL D) (paragraphs [0040], [0070]).
Mars discloses dynamically adjusting contention thresholds based on the application’s sensitivity, specifically teaching that the system is more willing to sacrifice utilization for lower-priority applications to protect higher-priority ones (col. 15, line 55-col. 16, line 15: the system handles contention response differently based on sensitivity, and is more willing to sacrifice utilization to eliminate contention for more sensitive/critical applications, and will adjust parameters of the approaches discussed herein to achieve these goas). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to formulate the sensitivity-based thresholding of Mars applied to the DAL-based cores of Fumey as a descending chain rule (thresholdA > thresholdB, > thresholdC > thresholdN). Expressing this relationship as a chain rule is merely a formal logical representation of the proportional threshold assignment already rendered obvious. The motivation would have been to scale the contention response across multiple applications of varying importance, thereby ensuring that the utilization of the least critical applications is sacrificed first to reduce the cross-core interference penalty experienced by the most critical applications (Mars col. 15, line 55-col. 16, line 15).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Fumey in view of Mars as applied to claim 7, and further in view of Miller et al. (US 8,943,287 B1, hereinafter Miller).
Regarding claim 10, Fumey in view of Mars does not disclose wherein the shared resource is connected to each of the plurality of processing cores via a crossbar connection. Miller discloses wherein the shared resource is connected to each of the plurality of processing cores via a crossbar connection (col. 1, lines 60-66: The method further includes configuring the multi-core processor unit to use the final set of schedules to control the execution of the partitions using at least two of the cores. The necessity to support hosted functions with differing design assurance levels (DAL) that require the scheduling of partitions maintains disjoint DAL level; col. 3, lines 46-53: A common access bus 30 interconnects the cores 12 and the memory system 22. The term "bus" as defined herein is meant to be interpreted broadly to include fabrics, traditional buses, cross-bar interconnects, and other subsystems that transfer data between components inside a computer, e.g. processing cores, memories, as known to those skilled in this field). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the connection between the processing cores and the shared resource in the Fumey and Mars system as a crossbar connection, as taught by Miller. The motivation would have been to provide a high-bandwidth, non-blocking communication path between the multiple processing cores and the shared memory, thereby reducing interconnect bottlenecks and efficiently supporting the strict partitioning and data transfer requirements of mixed-criticality (DAL) multi-core avionics systems.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
YÜKSE et al. (US 20220250766 A1) discloses “Two tasks are carried out in one step, which makes it impossible to assign a different priority or criticality to the different goals. In addition, a failure or erroneous behavior when achieving a goal with lower criticality (for example a secondary goal) can negatively affect solving a task with higher criticality (for example a primary goal)” (paragraph [0008]) and “It should be emphasized that the proposed idea provides an extremely advantageous separation of tasks according to their respective criticality, which can be used for assigning different design assurance levels (DAL) of functions with different criticalities and goals” (paragraph [0031]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISLEY N. KIM whose telephone number is (571)270-7832. The examiner can normally be reached M-F 11:30AM -7:30PM.
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/SISLEY N KIM/Primary Examiner, Art Unit 2196 9/5/2026
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