DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Warnick et al. (US 2018/0011180) in view of Zaghloul et al. (US 2004/0252059) all of record.
Warnick (e.g. Fig. 5) teaches printed circuit board (e.g. see [0130]) including:
Regarding Claim 1, and a Wilkinson power divider on the printed circuit board, wherein the Wilkinson power divider comprises coplanar waveguides (e.g. see Fig. 5 and [0130]).
Regarding Claim 2, wherein the Wilkinson power divider comprises a coplanar waveguide with ground (CPWG) device (e.g. see [00130]).
Regarding Claim 3, wherein the Wilkinson power divider is a two-way power divider (e.g. see Fig. 5, two outputs and one input).
Regarding Claim 9, wherein the device further comprises a plurality of stitching vias formed in the printed circuit board (e.g. see Fig. 5, vias are aligned along the sides of the coplanar lines to connect to ground to form the CPWG).
Regarding Claim 10, wherein stitching vias enclose at least the Wilkinson power divider (e.g. see in Fig. 5 the ground vias are on both sides surrounding the coplanar line in the same manner as present application’s Fig. 2).
However, Warnick does not teach that the CPWG divider is embedded (Claims 1-2), that the device further comprises one of more feed vias and one or more corresponding antipads formed in the printed circuit board (Claim 8).
Zaghloul (e.g. Fig. 2A) provides the general teaching of embedding a CPW Wilkinson divider (e.g. 230) in a printed circuit board (e.g. see [0013] and [0022], [0025] the layers 210, 214 ,and 240 can be printed thus the device stack 200 can be considered a printed circuit board and the divider chips (e.g. 230, 231, 232) are embedded in between the printed layers [0022] and [0025]) and using vias to connect to components on different layers (e.g. see [0013]).
It would have been considered obvious to one of ordinary skill in the art to have modified Warnick’s Wilkinson CPWG device to have been embedded in the circuit board and including feed vias connected to the divider such as generally taught by Zaghloul, because the embedded and layered device having connecting feed vias would have provided the advantageous benefit of integrating multiple circuitry elements with the Wilkinson divider to communicate together as an integrated system. Additionally, antipads around the vias would have been obvious because it is well-known that areas around vias need to have portions where the ground is missing/spaced (i.e. antipads) from the signaling feed via for the benefit of avoiding short circuiting of the feed via to ground which would make the circuitry fail to operate.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Warnick et al. (US 2018/0011180) in view of Zaghloul et al. (US 2004/0252059) as applied to claim 1 above, and further in view of Varonen et al. (US 2022/0166122) all of record.
The combination of Warnick and Zaghloul discloses an embedded Wilkinson device as described above, and Warnick teaches the device can operate in a wide GHz range (e.g. see [0127]).
However, Warnick does not appear to explicitly disclose the claimed range. Varonen, (e.g. [0052]) provides the general teaching a Wilkinson divider operating in all microwave frequencies.
It would have been considered obvious to one of ordinary skill in the art to have modified the combination of Warnick and Zaghloul to have operated in any selected portion of the full microwave range such as taught by Varonen including the microwave frequencies of 8GHz to 110GHz, because the selected range capabilities/operation would have been a mere design choice of known frequencies based on the use of the device such as is generally implied by Varonen.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Warnick et al. (US 2018/0011180) in view of Zaghloul et al. (US 2004/0252059) as applied to claim 1 above, and further in view of Lear et al. (US 2023/0187826) all of record.
The combination of Warnick and Zaghloul discloses an embedded Wilkinson device as described above. However, the combination does not explicitly teach the footprint size as in Claim 12.
Lear (e.g. [0003]) provides the general teaching that the transmission line sizes/footprints of power dividers is related to operating frequencies, as is fundamental characteristic of transmission lines.
It would have been considered obvious to one of ordinary skill in the art to have modified the footprint of the combination of Warnick and Zaghloul to have been within the claim 12 size, especially since the size of the divider footprint is a recognized result effective variable based on the frequencies of operation (as is recognized by Lear [0003] that transmission lines of dividers are sized according to frequency of operation), and thus minimizing size of the footprint would have been a mere optimization to minimize circuit real estate requirements of the device for which the minimum sizing/footprint is based on the selected operating frequency.
Claims 13-14 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Varonen et al. (US 2022/0166122) in view of Edenfield et al. (US 2019/0140362) all of record.
Varonen (e.g. Figs. 3-4) teaches a printed circuit board including:
Regarding Claim 13, a Wilkinson power divider (30) embedded in the printed circuit board (e.g. see Fig. 4, and the lines of the device can be stripline (e.g. see [0041]), and stripline is an embedded transmission line by definition), wherein the Wilkinson power divider comprises: an input trace (e.g. to Port 1); first and second output traces (e.g. to Ports 2/3); a first curved non-circular trace coupling the input trace to the first output trace at a first trace junction; a second curved non-circular trace coupling the input trace to the second output trace at a second trace junction (e.g. see the two respective curved portions in the central portion of the device 30); and a resistor (40) formed to be electrically connected between the first and second trace junctions.
Regarding Claim 14, wherein the traces are striplines (e.g. see [0041]).
Regarding claim 21, wherein the device is configured to operate from 8 GHz to 110 GHz (e.g. see [0052], the device can be for all microwave frequencies and 8 GHz to 110 GHz are microwaves)
However, Varonen does not teach that the resistor can be a foil (Claim 13).
Edenfield provides the general teaching that the resistor of a Wilkinson can be a resistor foil on the same plane as the other portions of the divider (e.g. [0040] and Fig. 14 and resistive foil 60).
It would have been considered obvious to one of ordinary skill in the art to have modified the Varonen device to have the resistor of Varonen to instead have been a resistor foil on the Wilkinson layer such as taught by Edenfield, because the resistive foil would have been a mere substitution of art-recognized equivalent resistor means for the same purpose of connecting between the outputs of a Wilkinson divider as is the same purpose in both Varonen and Edenfield.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Varonen et al. (US 2022/0166122) in view of Edenfield et al. (US 2019/0140362) as applied to claim 13 above, and further in view of Gendron et al. (US 2017/0005416) all of record.
The combination of Varonen and Edenfield teaches a device as described above.
However, the combination does not teach the specific ohms per square (OPS) such as 50 in Claims 16-17.
Gendron (e.g. see [0041]) provides the general teaching of the resistor of a Wilkinson can be 50 OPS.
It would have been considered obvious to one of ordinary skill in the art to have modified the generic unspecified resistor OPS of the combination to have been 50 OPS such as taught by Gendron, because it would have been a mere selection of a specific known OPS resistor characteristic for a Wilkinson divider for the unspecified OPS of the combination for which the resistors are for the same purpose of connecting between the outputs of a Wilkinson divider.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Varonen et al. (US 2022/0166122) in view of Edenfield et al. (US 2019/0140362) as applied to claim 13 above, and further in view of Warnick et al. (US 2018/0011180) all of record.
The combination of Varonen and Edenfield teaches a device as described above.
However, the combination does not teach that the stitching vias enclosing the power divider (Claims 19-20).
Warnick (e.g. Fig. 5) teaches forming a Wilkinson divider as a coplanar waveguide that is grounded (CPWG) using stitching vias.
It would have been considered obvious to one of ordinary skill in the art to have modified the combination of Varonen/Edenfield to have the Wilkinson divider be formed as a CPWG such as taught by Warnick, because the CPWG would have provided the advantageous benefits of making the device small (e.g. see Warnick [0128]) and the added fundamental benefit of additional shielding provided by the via wall/stitching adjacent the transmission lines.
Claims 18 is rejected under 35 U.S.C. 103 as being unpatentable over Varonen et al. (US 2022/0166122) in view of Edenfield et al. (US 2019/0140362) as applied to claim 13 above, and further in view of Zaghloul et al. (US 2004/0252059) all of record.
The combination of Varonen and Edenfield teaches a device as described above.
However, the combination does not teach that the device further comprises one of more feed vias and one or more corresponding antipads formed in the printed circuit board.
Zaghloul (e.g. Fig. 2A) provides the general teaching of embedding a CPW Wilkinson divider (e.g. 230) in a printed circuit board (e.g. see [0013] and [0022], [0025]) and using vias to connect to components on different layers (e.g. see [0013]).
It would have been considered obvious to one of ordinary skill in the art to have modified combination’s Wilkinson CPW device to have been embedded in the circuit board and including feed vias connected to the divider such as generally taught by Zaghloul, because the embedded and layered device having connecting feed vias would have provided the advantageous benefit of integrating multiple circuitry elements with the Wilkinson divider to communicate together as an integrated system. Additionally, antipads around the vias would have been obvious because it is well-known that areas around vias need to have portions where the ground is missing/spaced (i.e. antipads) from the signaling feed via for the benefit of avoiding short circuiting of the feed via to ground which would make the circuitry fail to operate.
Claims 22 is rejected under 35 U.S.C. 103 as being unpatentable over Varonen et al. (US 2022/0166122) in view of Edenfield et al. (US 2019/0140362) as applied to claim 13 above, and further in view of Lear et al. (US 2023/0187826) all of record.
The combination of Varonen and Edenfield teaches a device as described above.
However, the combination does not explicitly teach the footprint size as in Claim 22.
Lear (e.g. [0003]) provides the general teaching that the transmission line sizes/footprints of power dividers is related to operating frequencies, as is fundamental characteristic of transmission lines.
It would have been considered obvious to one of ordinary skill in the art to have modified the footprint of the combination to have been within the claim 22 size, especially since the size of the divider footprint is a recognized result effective variable based on the frequencies of operation (as is recognized by Lear [0003] that transmission lines of dividers are sized according to frequency of operation), and thus minimizing size of the footprint would have been a mere optimization to minimize circuit real estate requirements of the device for which the minimum sizing/footprint is based on the selected operating frequency.
Allowable Subject Matter
Claims 4-7 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
The arguments and/or amendments regarding Claims 4-7 and 15 are persuasive.
Applicant's arguments regarding Claims 1-3, 8-14 ,and 16-22 filed 3/13/26 have been fully considered but they are not persuasive.
Regarding Claim 1 (and Claims 2-3, 11), Applicant argues that Zaghloul is not a PCB fabrication reference and that the Wilkinson divider is on a chip thus is materially different from "a Wilkinson power divider embedded in the printed circuit board," as recited in claim 1, because the Wilkinson divider in Zaghloul et al. is described as on-chip (silicon/CMOS micromachining), not as a structure formed in or within a PCB laminate stack.
This argument is not persuasive. Zaghloul (e.g. Fig. 2A) teaches that the layers of the stack 200 include multiple printed layers (e.g. see [0013] and [0022], [0025] the layers 210, 214, and 240 can be printed thus the device stack 200 can be considered a printed circuit board and the divider chips (e.g. 230, 231, 232) are embedded in between the printed layers [0022] and [0025]). Since the divider chips are between printed layers such as layers 240 and 210 of the stack 200, the dividers can be considered embedded in the circuit board which has printed layers and thus 200 can be considered a printed circuit board as a whole.
Regarding Claims 12 and 22, Applicant argues that there is no evidence submitted by the Office Action regarding a power divider's footprint and the length of its transmission lines, nor is there any evidence of any specific transmission line length for a Wilkinson power divider that will fit within a footprint no greater than 100 mil x 80 mil.
This argument is not persuasive. Lear provides the general teaching that the sizing of transmission lines is tied to the selected operating frequency (e.g. see [0003]). The examiner further submits additional supporting evidence herewith. Yang et al. (e.g. see [0006]) (US 2018/0294777) further describes the fundamental well-known characteristic of transmission lines is that the length/size is fundamentally based on the frequency of operation (i.e. the size of transmission lines and thus minimum footprint or circuit real estate needed to form transmission lines such as Wilkinson divider transmission line circuits is dependent of the selected operating frequency). Accordingly, the footprint (i.e. circuit real estate) of the circuit in the combination is a result effective variable determining the minimum footprint needed which is based on the operating frequency to size the transmission lines of the Wilkinson divider to function at the selected frequency, and thus the minimizing the footprint size to a particular size such as claimed is an optimization as described in the rejections.
Regarding Claim 13 (and Claims 15-20), Applicant argues that Varonen teaches the resistor is in a chip on the substrate and not embedded in the substrate.
This argument is not persuasive as it is essentially arguing the Varonen reference alone rather than the combination. It is Edenfield which teaches a resistor of a Wilkinson divider can be on the same layer as the other portions of the divider. One of ordinary skill would clearly recognize that in the combination of Varonen and Edenfield, that the resistor could either be on the same layer as the rest of the Wilkinson such as taught by Edenfield or in a chip on an outer surface such as taught by Varonen since the resistors of Edenfield and Varonen are for the same intended purpose in a Wilkinson divider of being formed electrically between the first and second junctions of a divider. Furthermore, it should be noted that the claim does not explicitly say which parts are embedded and does not preclude having some of the claimed Wilkinson element portions to be outside the device as taught by Varonen.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHEN E JONES whose telephone number is (571)272-1762. The examiner can normally be reached 9AM to 5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached at 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Stephen E. Jones/Primary Examiner, Art Unit 2843
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