DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 19 March 2026 has been entered.
Election/Restrictions
Applicant’s election without traverse of Species I, corresponding to originally filed Figure 29, in the reply filed on 29 May 2025 is acknowledged.
Priority
This application is a Continuation-In-Part of Application No. 18/407,578, filed 09 January 2024, which references a Provisional Application No. 63/592,879. This application is also a Continuation-In-Part of Application No. 18/322,406, filed 23 May 2023, which references Provisional Application No. 63/416,896.
The claimed invention is directed to the embodiment of Figure 29 of the instant application. The embodiment of Figure 29 does not find support in any of the prior filed applications.
Therefore, the effective filing date of the claimed invention is 23 May 2024.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 31, 32, and 36-42 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by In (US 2023 / 0274687).
As pertaining to Claim 31, In discloses (see Fig. 25) a display gate driver circuit (see Page 5, Para. [0085]) comprising:
a shift register subcircuit (SST1, SST2) configured to receive shift register clock signals (CLK1, CLK2, CLK4) wherein the shift register subcircuit (SST1, SST2) includes a transistor (T7) having a first source-drain terminal (i.e., a lower terminal) configured to receive one of the shift register clock signals (CLK2, CLK4) and a second source-drain terminal (i.e., an upper terminal) on which a carry out signal is produced (see (CR1) and note that (CR1) is produced from (VGH) and (CLK2); see Page 5, Para. [0099]); and
an output buffer subcircuit (SST3b) configured to receive an output buffer clock signal (CLK2, CLK4) and to generate a corresponding gate output signal (OUT1b, SL1b), wherein the output buffer subcircuit (SST3b) comprises:
a first output buffer transistor (T17) having a first source-drain terminal (i.e., a lower terminal) configured to receive the output buffer clock signal (CLK2, CLK4) and a second source-drain terminal (i.e., an upper terminal) on which the gate output signal (OUT1b, SL1b) is generated; and
a second output buffer transistor (T16) having a drain terminal (i.e., a lower terminal) coupled to the first output buffer transistor (T17), a source terminal (i.e., an upper terminal) configured to receive a power supply voltage (VGH), and a gate terminal directly coupled to a gate terminal of the transistor (T7) in the shift register subcircuit (see (SST1, SST2); and see Page 17, Para. [0322]-[0324] in combination with Fig. 24; Page 5, Para. [0087]; Page 6, Para. [0119]-[0120]; Page 12, Para. [0226]; Page 12, Para. [0233]; and Page 13, Para. [0249]-[0252]).
As pertaining to Claim 32, In discloses (see Fig. 25) that the shift register subcircuit (SST1, SST2) comprises an inverter (SST3a_1) having an n-type semiconducting oxide transistor (T10_1) and a p-type silicon transistor (T9) coupled together in series (see Page 7, Para. [0126]-0130]).
As pertaining to Claim 36, In discloses (see Fig. 25) that the first output buffer transistor (T17) comprises a p-type silicon transistor (Page 13, Para. [0252]).
As pertaining to Claim 37, In discloses (see Fig. 25) that the output buffer subcircuit (SST3b) further comprises:
a capacitor (C2) having a first terminal (i.e., a lower terminal) coupled to a gate terminal of the first output buffer transistor (T17) and having a second terminal (i.e., an upper terminal) coupled to the second source-drain terminal (i.e., the upper terminal) of the first output buffer transistor (T17; see Page 7, Para. [0123] and Page 13, Para. [0251]).
As pertaining to Claim 38, In discloses (see Fig. 25) that the output buffer subcircuit (SST3b) further comprises:
a third transistor (T2) having a first source-drain terminal (i.e., a lower terminal) coupled to the gate terminal of the first output buffer transistor (T17), a second source-drain terminal (i.e., an upper terminal) coupled to the shift register subcircuit (SST1, SST2), and a gate terminal configured to receive the power supply voltage (VGH; see Page 6, Para. [0111]).
As pertaining to Claim 39, In discloses (see Fig. 25) that the shift register subcircuit (SST1, SST2) further comprises:
an inverter (SST3a_1) having an n-type semiconducting oxide transistor (T10_1) and a p-type silicon transistor (T9) coupled together in series (see Page 7, Para. [0126]-0130]).
As pertaining to Claim 40, In discloses (see Fig. 25) that the shift register subcircuit (SST1, SST2) further comprises:
an additional transistor (T3) having a drain terminal (i.e., an upper terminal) coupled to the transistor (T7), a source terminal (i.e., a lower terminal) configured to receive an additional power supply voltage (i.e., a voltage of (SSP)) different than the power supply voltage (VGH), and a gate terminal output to (i.e., via path (T8, T7, T9)) an output of the inverter (SST3a_1; see Page 6, Para. [0112]).
As pertaining to Claim 41, In discloses (see Fig. 25) that the shift register subcircuit (SST1, SST2) further comprises:
a first capacitor (C1) coupled between the gate terminal and the second source-drain terminal (i.e., the upper terminal) of the transistor (T7; Page 6, Para. [0116]).
As pertaining to Claim 42, In discloses (see Fig. 25) that the shift register subcircuit (SST1, SST2) further comprises:
a second capacitor (C2) coupled between the gate terminal and the source terminal (i.e., the lower terminal) of the additional transistor (T3; Page 7, Para. [0123]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 8, 26-27, and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang (US 12,183,266) in view of Kim et al. (hereinafter “Kim” US 2021 / 0287585).
As pertaining to Claim 1, Zhang discloses (see Fig. 50) a display gate driver circuit (see Col. 1, Ln. 17-20) comprising:
a shift register subcircuit (10, 20, 30, 50, 70, 71, 90) configured to receive shift register clock signals (CK, XCK, STV, Nout, RST, RST2, VGH, VGL, O) and to produce a carry out signal (Nout), wherein the shift register subcircuit (10, 20, 30, 50, 70, 71, 90) comprises an inverter (70) having an n-type transistor (T10) and a p-type transistor (T9) connected in series; and
an output buffer subcircuit (40, 60, 80) configured to receive an output buffer clock signal (CK) and to generate a corresponding gate output signal (Pout), wherein the output buffer subcircuit (40, 60, 80) comprises:
a first output buffer transistor (T6) having a first source-drain terminal (i.e., an upper terminal) configured to receive the output buffer clock signal (CK) and a second source-drain terminal (i.e., a lower terminal) on which the gate output signal (Pout) is generated; and
a second output buffer transistor (T7) having a drain terminal (i.e., an upper terminal) coupled to the first output buffer transistor (T6), a source terminal (i.e., a lower terminal) configured to receive a power supply voltage (VGH), and a gate terminal coupled (i.e., via (T1, T15)) to a gate terminal of the n-type transistor (T10; see Col. 6, Ln. 27-57; Col. 7, Ln. 3-8, Ln. 28-40, and Ln. 44-51; Col. 8, Ln. 4-12; Col. 9, Ln. 12-13 and Ln. 41-57; Col. 10, Ln. 10-17, Ln. 22-39, and Ln. 45-67 through Col. 11, Ln. 1-9, Ln. 15-24, and Ln. 28-40; and Col. 17, Ln. 4-11 for a general description of Fig. 50).
While semiconducting oxide transistors and/or silicon transistors are well-known and have been fully implemented in the art, Zhang does not explicitly state that the display gate driver circuit is implemented using semiconducting oxide transistors and/or silicon transistors.
However, in the same field of endeavor, Kim discloses (see Fig. 5) that it was well-known in the art to implement a display gate driver circuit (STn) comprising a shift register subcircuit (510, 520, 530) and an inverter (see (TP2, TP3, TP6, TP7, TP8)), in combination with an output buffer subcircuit (540, 550) comprising a first output buffer transistor (TN6) and a second output buffer transistor (TN5), wherein the display gate driver circuit (STn) comprises any combination of p-type and n-type transistors that are implemented using semiconducting oxide transistors and/or silicon transistors (Page 3 through Page 4, Para. [0045]-[0046] with Page 7, Para. [0108] and Page 8, Para. [0128]; and see Page 7, Para. [0105]-[0111] and [0113]-[0117]; Page 8, Para. [0119]-[0120], [0128]-[0130], and [0132]; and Page 9, Para. [0141]-[0143] for a general description of Fig. 5). It is a general goal of Kim to provide a gate driver circuit that allows for reduced dead space and lower production cost (see Page 11 through Page 12, Para. [0183]). Further, Kim expressly suggests that the implementation of a display gate driver circuit using semiconducting oxide transistors and/or silicon transistors can provide minimized current leakage in the driver circuit (see Page 1, Para. [0003]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhang with the teachings of Kim, such that the shift register subcircuit (10, 20, 30, 50, 70, 71, 90) of Zhang comprises an inverter (70) having an n-type semiconducting oxide transistor (T10) and a p-type silicon transistor (T9) connected in series, as suggested by Kim, in order to provide a display gate driver circuit with reduced production cost using known device structures that provide for minimized current leakage in the driver circuit.
As pertaining to Claim 3, Zhang discloses (see Fig. 50) that the output buffer subcircuit (40, 60, 80) further comprises:
a capacitor (C1) having a first terminal (i.e., an upper terminal) coupled to a gate terminal of the first output buffer transistor (T6) and having a second terminal (i.e., a lower terminal) coupled to the second source-drain terminal (i.e., the lower terminal) of the first output buffer transistor (T6); and
a third transistor (T8) having a first source-drain terminal (i.e., a right terminal) coupled to the gate terminal of the first output buffer transistor (T6), a second source-drain terminal (i.e., a left terminal) coupled to the shift register subcircuit (10, 20, 30, 50, 70, 71, 90), and a gate terminal configured to receive the power supply voltage (i.e., the high voltage VGH; again, see Col. 7, Ln. 44-51; Col. 9, Ln. 12-13; and Col. 16, Ln. 61-64; and note that (RST2) can be the positive gate driving signal VGH).
As pertaining to Claim 8, Zhang discloses (see Fig. 51) that the output buffer clock signal (CK) is driven high before a given pulse (XCK) of one of the shift register clock signals (CK, XCK, STV, Nout, RST, RST2, VGH, VGL, O) and driven low during the given pulse (XCK; see Col. 21, Ln. 57-67 through Col. 22, Ln. 1-15).
As pertaining to Claim 26, Zhang discloses (see Fig. 51) that the output buffer clock signal (CK) is asserted and then deasserted during a given pulse (XCK) of one of the shift register clock signals (see Col. 21, Ln. 57-67 through Col. 22, Ln. 1-15).
As pertaining to Claim 27, Zhang discloses (see Fig. 50) that the first output buffer transistor (T6) comprises a p-type silicon transistor (see Col. 9, Ln. 12-13).
As pertaining to Claim 30, Zhang discloses (see Fig. 50) that the output buffer subcircuit (40, 60, 80) further comprises:
a third transistor (T8) having a first source-drain terminal (i.e., a right terminal) coupled to the gate terminal of the first output buffer transistor (T6), a second source-drain terminal (i.e., a left terminal) coupled to the shift register subcircuit (10, 20, 30, 50, 70, 71, 90), and a gate terminal configured to receive the power supply voltage (i.e., the high voltage VGH; again, see Col. 7, Ln. 44-51; Col. 9, Ln. 12-13; and Col. 16, Ln. 61-64; and note that (RST2) can be the positive gate driving signal VGH).
Claims 2, 7, and 28-29 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Kim and further in view of Kawashima et al. (hereinafter “Kawashima” US 2022 / 0406818).
As pertaining to Claim 2, the combined teachings of Zhang and Kim disclose (see Fig. 50 of Zhang) that the first output buffer transistor (T6) comprises a p-type silicon transistor (i.e., a thin film transistor), and wherein the second output buffer transistor (T7) comprises a semiconducting oxide transistor (i.e., a thin film transistor; see Col. 9, Ln. 39-40; Col. 10, Ln. 5-9 and Ln. 53-56; and see Page 3 through Page 4, Para. [0045]-[0046] with Page 7, Para. [0108] and Page 8, Para. [0128] of Kim).
Neither Zhang nor Kim explicitly discloses that the second output buffer transistor has an additional gate terminal shorted to its source terminal or configured to receive an adjustable voltage.
However, in the same field of endeavor, Kawashima discloses (see Fig. 4A) a display gate driver circuit analogous to that disclosed by Zhang and Kim, wherein an output buffer subcircuit (11), implemented using silicon transistors and/or semiconducting oxide transistors (see Page 3, Para. [0062]), is configured to generate a gate output signal (SROUT) and comprises a first output buffer transistor (22) and a second output buffer transistor (21), wherein the second output buffer transistor (21) has a drain terminal (i.e., an upper terminal) coupled to the first output buffer transistor (22), a source terminal (i.e., a lower terminal) configured to receive a power supply voltage (VSS), and a gate terminal coupled to a gate terminal of a semiconducting oxide transistor (46) of an inverting circuit (41, 46) of a shift register subcircuit (13), and an additional gate terminal shorted to its source terminal (i.e., the lower terminal) or configured to receive an adjustable voltage (VSS; see Page 6, Para. [0091]-[0095]; and Page 7 through Page 8, Para. [0108], [0110]-[0111], and [0113]-[0115]). It is a goal of Kawashima to provide a highly reliable display gate driver circuit with highly reliable semiconductor devices that can be manufactured at low cost (see Page 1, Para. [0007]). In this regard, Kawashima specifically suggests the implementation of a second output buffer transistor having dual gate terminals, with a first gate terminal coupled to a gate terminal of a semiconducting oxide transistor of a shift register subcircuit and an additional gate terminal shorted to its source terminal or configured to receive an adjustable voltage, in order to inhibit a shift in the threshold voltage of the second output buffer transistor and thereby increase the performance and reliability of the display gate driver circuit (see Page 6, Para. [0093]-[0094]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhang and Kim with the teachings of Kawashima, such that the first output buffer and the second output buffer are implemented using silicon transistors and/or semiconducting oxide transistors, and the second output buffer transistor (T7) has an additional gate terminal shorted to its source terminal or configured to receive an adjustable voltage, as suggested by Kawashima, in order to inhibit a shift in the threshold voltage of the second output buffer transistor and thereby increase the performance and reliability of the display gate driver circuit and thereby produce a highly reliable display gate driver circuit with highly reliable semiconductor devices that can be manufactured at low cost.
As pertaining to Claim 7, Zhang discloses (see Fig. 50) that the n-type semiconducting oxide transistor (T10) comprises a drain terminal (i.e., an upper terminal) coupled to the p-type silicon transistor (T9), a source terminal (i.e., a lower terminal) configured to receive a power supply voltage (VGL), and a first gate terminal (see Col. 10, Ln. 60-67 through Col. 11, Ln. 1-9).
Zhang does not explicitly show that the source terminal of the n-type semiconducting oxide transistor (T10) comprises a source terminal that receives the same power supply voltage (VGH) as the source terminal of the second output buffer transistor (T7). That is, Zhang discloses that the source terminal of the second output buffer transistor (T7) receives a high power supply voltage (VGH) while the source terminal of the n-type semiconducting oxide transistor (T10) receives a low power supply volage (VGL).
However, one of ordinary skill in the art would have readily recognized that the power supply voltage received by the source terminal of the second output buffer transistor (T7) is merely a resulting feature of driving the on/off states of an n-type transistor or a p-type transistor in an associated pixel circuit. That is, Zhang discloses (see Fig. 1) that the second output buffer transistor (T7; see Fig. 50) provides on/off driving voltages to a p-type transistor (T2P; see Fig. 1), wherein the high power supply voltage (VGH) serves as an off voltage for the p-type transistor (T2P). In this regard, Zhang explicitly discloses that the power supply voltage should be a low power supply voltage (VGL) to turn off an n-type transistor and should be a high power supply voltage (VGH) to turn off a p-type transistor (see Col. 10, Ln. 5-9). Likewise, Kim explicitly discloses (see Fig. 5) that a second output buffer transistor (TP4) driving an off state of a p-type transistor (TR2; see Fig. 2) in a pixel circuit (PX) receives a high power supply voltage (VGH) at a source terminal (see (TP4) outputting high power supply voltage (VGH) at (GWP)), while a second output buffer transistor (TN5) driving an off state of an n-type transistor (TR3; see Fig. 2) in a pixel circuit (PX) receives a low power supply voltage (VGL) at a source terminal (see (TN5) outputting low power supply voltage (VGL) at (GWN); see Page 4, Para. [0056]-[0057]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the source terminal of the n-type semiconducting oxide transistor (T10) disclosed by Zhang is configured to receive the same power supply voltage (VGL) as the source terminal of the second output buffer transistor (T7), merely as a resulting feature of driving the on/off states of an n-type transistor (i.e., (TP2) in Fig. 1) in an associated pixel circuit. That is, one of ordinary skill in the art would have recognized that the source terminal of the second output buffer transistor (T7) can be a high power supply voltage (VGH) or a low power supply voltage (VGL) depending on whether the transistor driven by the output buffer circuit is an n-type transistor or a p-type transistor and, as such, the source terminal of the n-type semiconducting oxide transistor (T10) is configured to receive the same power supply voltage (VGL) as the source terminal of the second output buffer transistor (T7).
Still, neither Zhang nor Kim explicitly discloses that the n-type semiconducting oxide transistor comprises a second gate terminal shorted to its source terminal.
However, in the same field of endeavor, Kawashima discloses (see Fig. 4A) a display gate driver circuit analogous to that disclosed by Zhang and Kim, wherein a number of transistors are provided (see (21) and (46), for example) with a second gate terminal shorted to its source terminal (see Page 6, Para. [0091]-[0095]; and Page 7, Para. [0113]-[0114]). It is a goal of Kawashima to provide a highly reliable display gate driver circuit with highly reliable semiconductor devices that can be manufactured at low cost (see Page 1, Para. [0007]). In this regard, Kawashima specifically suggests the implementation of transistors having dual gate terminals, with a second gate terminal shorted to its source terminal, in order to inhibit a shift in the threshold voltage of the second output buffer transistor and thereby increase the performance and reliability of the display gate driver circuit (see Page 6, Para. [0093]-[0094]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhang and Kim with the teachings of Kawashima, such that the n-type semiconducting oxide transistor comprises a second gate terminal shorted to its source terminal, as suggested by Kawashima, in order to inhibit a shift in the threshold voltage of the n-type semiconducting oxide transistor and thereby increase the performance and reliability of the display gate driver circuit and thereby produce a highly reliable display gate driver circuit with highly reliable semiconductor devices that can be manufactured at low cost.
As pertaining to Claim 28, the combined teachings of Zhang and Kim disclose (see Fig. 50 of Zhang) that the second output buffer transistor (T7) comprises a semiconducting oxide transistor (i.e., a thin film transistor; see Col. 9, Ln. 39-40; Col. 10, Ln. 5-9 and Ln. 53-56; and see Page 3 through Page 4, Para. [0045]-[0046] with Page 7, Para. [0108] and Page 8, Para. [0128] of Kim).
Neither Zhang nor Kim explicitly discloses that the second output buffer transistor has an additional gate terminal shorted to its source terminal.
However, in the same field of endeavor, Kawashima discloses (see Fig. 4A) a display gate driver circuit analogous to that disclosed by Zhang and Kim, wherein an output buffer subcircuit (11), implemented using silicon transistors and/or semiconducting oxide transistors (see Page 3, Para. [0062]), is configured to generate a gate output signal (SROUT) and comprises a first output buffer transistor (22) and a second output buffer transistor (21), wherein the second output buffer transistor (21) has a drain terminal (i.e., an upper terminal) coupled to the first output buffer transistor (22), a source terminal (i.e., a lower terminal) configured to receive a power supply voltage (VSS), and a gate terminal coupled to a gate terminal of a semiconducting oxide transistor (46) of an inverting circuit (41, 46) of a shift register subcircuit (13), and an additional gate terminal shorted to its source terminal (i.e., the lower terminal; see Page 6, Para. [0091]-[0095]; and Page 7 through Page 8, Para. [0108], [0110]-[0111], and [0113]-[0115]). It is a goal of Kawashima to provide a highly reliable display gate driver circuit with highly reliable semiconductor devices that can be manufactured at low cost (see Page 1, Para. [0007]). In this regard, Kawashima specifically suggests the implementation of a second output buffer transistor having dual gate terminals, with a first gate terminal coupled to a gate terminal of a semiconducting oxide transistor of a shift register subcircuit and an additional gate terminal shorted to its source terminal, in order to inhibit a shift in the threshold voltage of the second output buffer transistor and thereby increase the performance and reliability of the display gate driver circuit (see Page 6, Para. [0093]-[0094]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhang and Kim with the teachings of Kawashima, such that the first output buffer and the second output buffer are implemented using silicon transistors and/or semiconducting oxide transistors, and the second output buffer transistor (T7) has an additional gate terminal shorted to its source terminal, as suggested by Kawashima, in order to inhibit a shift in the threshold voltage of the second output buffer transistor and thereby increase the performance and reliability of the display gate driver circuit and thereby produce a highly reliable display gate driver circuit with highly reliable semiconductor devices that can be manufactured at low cost.
As pertaining to Claim 29, the combined teachings of Zhang and Kim disclose (see Fig. 50 of Zhang) that the second output buffer transistor (T7) comprises a semiconducting oxide transistor (i.e., a thin film transistor; see Col. 9, Ln. 39-40; Col. 10, Ln. 5-9 and Ln. 53-56; and see Page 3 through Page 4, Para. [0045]-[0046] with Page 7, Para. [0108] and Page 8, Para. [0128] of Kim).
Neither Zhang nor Kim explicitly discloses that the second output buffer transistor has an additional gate terminal configured to receive an adjustable voltage.
However, in the same field of endeavor, Kawashima discloses (see Fig. 4A) a display gate driver circuit analogous to that disclosed by Zhang and Kim, wherein an output buffer subcircuit (11), implemented using silicon transistors and/or semiconducting oxide transistors (see Page 3, Para. [0062]), is configured to generate a gate output signal (SROUT) and comprises a first output buffer transistor (22) and a second output buffer transistor (21), wherein the second output buffer transistor (21) has a drain terminal (i.e., an upper terminal) coupled to the first output buffer transistor (22), a source terminal (i.e., a lower terminal) configured to receive a power supply voltage (VSS), and a gate terminal coupled to a gate terminal of a semiconducting oxide transistor (46) of an inverting circuit (41, 46) of a shift register subcircuit (13), and an additional gate terminal configured to receive an adjustable voltage (VSS; see Page 6, Para. [0091]-[0095]; and Page 7 through Page 8, Para. [0108], [0110]-[0111], and [0113]-[0115]). It is a goal of Kawashima to provide a highly reliable display gate driver circuit with highly reliable semiconductor devices that can be manufactured at low cost (see Page 1, Para. [0007]). In this regard, Kawashima specifically suggests the implementation of a second output buffer transistor having dual gate terminals, with a first gate terminal coupled to a gate terminal of a semiconducting oxide transistor of a shift register subcircuit and an additional gate terminal configured to receive an adjustable voltage, in order to inhibit a shift in the threshold voltage of the second output buffer transistor and thereby increase the performance and reliability of the display gate driver circuit (see Page 6, Para. [0093]-[0094]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Zhang and Kim with the teachings of Kawashima, such that the first output buffer and the second output buffer are implemented using silicon transistors and/or semiconducting oxide transistors, and the second output buffer transistor (T7) has an additional gate terminal configured to receive an adjustable voltage, as suggested by Kawashima, in order to inhibit a shift in the threshold voltage of the second output buffer transistor and thereby increase the performance and reliability of the display gate driver circuit and thereby produce a highly reliable display gate driver circuit with highly reliable semiconductor devices that can be manufactured at low cost.
Claims 34-35 are rejected under 35 U.S.C. 103 as being unpatentable over In in view of Kawashina.
As pertaining to Claim 34, In discloses (see Fig. 25) that the second output buffer transistor (T16) comprises a semiconducting oxide transistor (see Page 13, Para. [0249]-[0252]).
In does not explicitly disclose that the second output buffer transistor has an additional gate terminal shorted to its source terminal.
However, in the same field of endeavor, Kawashima discloses (see Fig. 4A) a display gate driver circuit analogous to that disclosed by In, wherein an output buffer subcircuit (11), implemented using silicon transistors and/or semiconducting oxide transistors (see Page 3, Para. [0062]), is configured to generate a gate output signal (SROUT) and comprises a first output buffer transistor (22) and a second output buffer transistor (21), wherein the second output buffer transistor (21) has a drain terminal (i.e., an upper terminal) coupled to the first output buffer transistor (22), a source terminal (i.e., a lower terminal) configured to receive a power supply voltage (VSS), and a gate terminal coupled to a gate terminal of a semiconducting oxide transistor (46) of an inverting circuit (41, 46) of a shift register subcircuit (13), and an additional gate terminal shorted to its source terminal (i.e., the lower terminal; see Page 6, Para. [0091]-[0095]; and Page 7 through Page 8, Para. [0108], [0110]-[0111], and [0113]-[0115]). It is a goal of Kawashima to provide a highly reliable display gate driver circuit with highly reliable semiconductor devices that can be manufactured at low cost (see Page 1, Para. [0007]). In this regard, Kawashima specifically suggests the implementation of a second output buffer transistor having dual gate terminals, with a first gate terminal coupled to a gate terminal of a semiconducting oxide transistor of a shift register subcircuit and an additional gate terminal shorted to its source terminal, in order to inhibit a shift in the threshold voltage of the second output buffer transistor and thereby increase the performance and reliability of the display gate driver circuit (see Page 6, Para. [0093]-[0094]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of In with the teachings of Kawashima, such that the first output buffer and the second output buffer are implemented using silicon transistors and/or semiconducting oxide transistors, and the second output buffer transistor (T16) has an additional gate terminal shorted to its source terminal, as suggested by Kawashima, in order to inhibit a shift in the threshold voltage of the second output buffer transistor and thereby increase the performance and reliability of the display gate driver circuit and thereby produce a highly reliable display gate driver circuit with highly reliable semiconductor devices that can be manufactured at low cost.
As pertaining to Claim 35, In discloses (see Fig. 25) that the second output buffer transistor (T16) comprises a semiconducting oxide transistor (see Page 13, Para. [0249]-[0252]).
In does not explicitly disclose that the second output buffer transistor has an additional gate terminal configured to receive an adjustable voltage.
However, in the same field of endeavor, Kawashima discloses (see Fig. 4A) a display gate driver circuit analogous to that disclosed by In, wherein an output buffer subcircuit (11), implemented using silicon transistors and/or semiconducting oxide transistors (see Page 3, Para. [0062]), is configured to generate a gate output signal (SROUT) and comprises a first output buffer transistor (22) and a second output buffer transistor (21), wherein the second output buffer transistor (21) has a drain terminal (i.e., an upper terminal) coupled to the first output buffer transistor (22), a source terminal (i.e., a lower terminal) configured to receive a power supply voltage (VSS), and a gate terminal coupled to a gate terminal of a semiconducting oxide transistor (46) of an inverting circuit (41, 46) of a shift register subcircuit (13), and an additional gate terminal shorted to its source terminal (i.e., the lower terminal) and configured to receive an adjustable voltage (see Page 6, Para. [0091]-[0095]; and Page 7 through Page 8, Para. [0108], [0110]-[0111], and [0113]-[0115]). It is a goal of Kawashima to provide a highly reliable display gate driver circuit with highly reliable semiconductor devices that can be manufactured at low cost (see Page 1, Para. [0007]). In this regard, Kawashima specifically suggests the implementation of a second output buffer transistor having dual gate terminals, with a first gate terminal coupled to a gate terminal of a semiconducting oxide transistor of a shift register subcircuit and an additional gate terminal shorted to its source terminal and configured to receive an adjustable voltage, in order to inhibit a shift in the threshold voltage of the second output buffer transistor and thereby increase the performance and reliability of the display gate driver circuit (see Page 6, Para. [0093]-[0094]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of In with the teachings of Kawashima, such that the first output buffer and the second output buffer are implemented using silicon transistors and/or semiconducting oxide transistors, and the second output buffer transistor (T16) has an additional gate terminal shorted to its source terminal and configured to receive an adjustable voltage, as suggested by Kawashima, in order to inhibit a shift in the threshold voltage of the second output buffer transistor and thereby increase the performance and reliability of the display gate driver circuit and thereby produce a highly reliable display gate driver circuit with highly reliable semiconductor devices that can be manufactured at low cost.
Allowable Subject Matter
Claims 4-6 and 33 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: none of the references relied upon by the examiner, considered alone or in reasonable combination, teach or fairly suggest the combination of structural features recited in Claims 1 and 3, in combination with the features of dependent Claim 4. Dependent Claims 5 and 6 are allowable due to their dependency from Claim 4. Likewise, none of the references relied upon by the examiner, considered alone or in reasonable combination, teach or fairly suggest the combination of structural features recited in Claims 31 and 32, in combination with the features of dependent Claim 33.
Response to Arguments
Applicant’s arguments with respect to Claims 1-8 and 26-42 have been considered but are moot because the new ground of rejection does not rely on a combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The applicant has argued that the teachings of Kim and Kawashima, as relied upon by the examiner in the Final Rejection mailed 10 February 2026, do not provide for the claimed “inverter” as newly recited in Claims 1-8 and 26-30, and/or the claimed “transistor” as newly recited in the Claims 31-42 (see Remark at Pages 9 through 11). Respectfully, the applicant’s argument is moot in view of at least the teachings of Zhang and In as newly relied upon in the above rejections.
Therefore, the rejection of Claims 1-3, 7-8, 26-32, and 34-42 is maintained. Claims 4-6 and 33 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ohkawa et al. (US 2012 / 0092311) and Furuta et al. (US 2014 / 0168181) disclose shift register circuits implementing inverter circuits that are pertinent to the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON M MANDEVILLE whose telephone number is (571)270-3136. The examiner can normally be reached Mon - Fri 7:30AM-4:00PM.
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/JASON M MANDEVILLE/Primary Examiner, Art Unit 2623
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