DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 2, 7, 9, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hseih et al US Publication 2016/0165159 in view of Cremers US Publication 2020/0204750.
Regarding claim 1 Hseih et al discloses of Fig. 1 – 8 of applicant’s a solid-state imaging device comprising a pixel part including pixels arranged therein (paragraph 0036 a solid-state image sensor has pixels); wherein the pixels each include a photoelectric conversion film converting light into a photogenerated current and a semiconductor pixel circuit (paragraph 0086 – 0089 3D stacked CMOS image sensor depicts distinct layers of the 3D stacked CMOS image sensor where the first layer 505 comprises a BSI sensor layer with photodiodes and the second (middle) layer 506 comprise the analog front end (AFE) and A/D conversion circuitry and where based on the light to which they are exposed the photodiodes PD1-PD3 generate current signals such that the pixels each include a PD photoelectric conversion film first layer 505 converting light into a photogenerated current and a second (middle) layer 506 semiconductor pixel circuit); wherein the photoelectric conversion film and the semiconductor pixel circuit are stacked and electrically coupled to each other within the pixel (paragraph 0089 PD1 signals on first layer 505 are transferred to the pixel circuitry of the second layer 506 via the fine-pitch hybrid bonds such that the PD photoelectric conversion on first layer 505 and the semiconductor pixel circuit on second layer 506 are stacked and electrically coupled to each other via the fine-pitch hybrid bonds within the pixel);
Hseih et al further discloses of applicant’s wherein the photoelectric conversion film has an sensitivity (paragraph 0038 photodiodes include one photodiode used to detect a red, green, and blue component of incoming light sensitivity); and wherein the semiconductor pixel circuit includes a pixel analog circuit detecting the photogenerated current (paragraph 0089 – 0090 photodiodes generate current signals received via the fine-pitch hybrid bonds to the second layer 506 as the analog front end (AFE) such that the semiconductor pixel circuit second layer 506 includes a pixel analog front end circuit detecting the photogenerated current); and a pixel analog-to-digital (AD) conversion circuit converting an analog signal from the pixel analog circuit to a digital signal (paragraph 0090 the second level 556 has analog digital conversion (ADC) layer and (claim 25) analog to digital converter converts the amplifier signal into a digital signal such that pixel analog-to-digital (AD) conversion circuit converting an amplifier analog signal from the pixel analog front end circuit, on semiconductor pixel circuit second layer 506, to a digital signal);
Hseih et al discloses a stacked imager circuit with photodiodes on a first layer but does not expressively disclose the photoelectric conversion film has an infrared sensitivity;
Cremers teaches infrared wavelength sensitive pixels in an array. Cremers teaches of Fig. 1 – 6 of applicant’s the photoelectric conversion film has an infrared sensitivity (paragraph 0017 – 0019 pixel 30 include a photosensitive element such as photodiode 22 where color filter elements configure image pixel 30 to detect light of infrared wavelength such that the pixel 30 photoelectric conversion film has an infrared sensitivity). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the circuitry of Hseih et al in a manner similar to Cremers. Doing so would result in improving Hseih et al invention in a similar way as Cremers - namely the ability to provide infrared wavelength sensitive pixels in an array, in Cremers invention, to the stacked imager circuit with photodiodes on a first layer in Hseih et al invention.
Regarding claim 2 of the combination of Hseih et al in view of Cremers, Cremers further teaches of applicant’s wherein the pixels each include: a pixel digital memory recording the digital signal from the pixel AD conversion circuit; and a pixel digital reading circuit reading out the digital signal from the pixel digital memory (claim 25 analog to digital converter converts the amplifier signal into a digital signal. Paragraph 0012 - 0013 digital image data to be provided to storage and processing circuitry 18. Storage and processing circuitry 18 has storage for image data that has been captured by camera module 12 image sensors 16 and is stored using processing circuitry 18 and where the processed image data is provided to external equipment connected to processing circuitry 18 such that the pixel image sensor 16 each include a pixel digital memory in processing circuitry 18 for recording the digital signal from the pixel AD conversion circuit producing digital image data and processing circuitry 18 is a pixel digital reading circuit reading out the digital signal from the pixel digital memory in processing circuitry 18 and providing the digital image data to external equipment connected to processing circuitry 18).
Regarding claim 7 of the combination of Hseih et al in view of Cremers, Cremers further teaches of applicant’s wherein the pixel AD conversion circuit is shared by the multiple pixels (paragraph 0015 image readout circuitry 48 receives image signals (e.g., analog pixel values generated by pixels 30) over column lines 42. Image readout circuitry 48 includes analog-to-digital conversion (ADC) circuitry such that the pixel AD conversion circuit is shared by the multiple pixels as seen in Fig. 4).
Regarding claim 9, claim 9 is rejected for being fully encompassed by the reasons found in rejected claim 1 above and where of the combination of Hseih et al in view of Cremers, Hseih et al further teaches the additional claim limitation of applicant's a method for manufacturing a solid-state imaging device (paragraph 0009 a method of manufacturing a three dimensional (3D) stacked image sensor); forming the pixels by a photoelectric conversion film (paragraph 0086 3D stacked CMOS pixel image sensor with photodiode wafer with photodiodes PD1-PD3 from the shared-pixels architectures is forming the pixels by a photoelectric conversion layer film); forming, in the semiconductor pixel circuit, a pixel analog circuit (paragraph 0087 – 0090 second (middle) layer 506 has the analog front end (AFE) and has analog digital conversion (ADC) layer such that a pixel analog front end circuit in the second (middle) layer 506 semiconductor pixel circuit is formed).
Regarding claim 10 of the combination of Hseih et al in view of Cremers, Cremers further teaches of applicant’s an electronic apparatus comprising: and an optical system for forming a subject image on the solid-state imaging device (paragraph 0012 electronic device has lens 14 where light from a scene may be focused onto image sensor 16 by lenses 14 where lens 14 is an optical system for forming a subject image on the solid-state imaging device 16).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hseih et al US Publication 2016/0165159 in view of Cremers US Publication 2020/0204750 as applied to claim 2 above, and further in view of Ganguly et al US Publication 2018/0227518.
Regarding claim 3 the combination of Hseih et al in view of Cremers teaches a stacked imager circuit with a second layer analog circuit but do not expressively teach wherein the pixel analog circuit includes: an in-pixel feedback circuit keeping a voltage applied to the photoelectric conversion film at a constant level; and an in-pixel integrator circuit integrating and converting the photogenerated current into a voltage and a pixel initialization circuit initializing the integrator circuit;
Ganguly et al teaches an imager circuit with operational amplifier arrangement as an integrator that can be reset. Ganguly et al teaches of Fig. 1 – 6 of applicant’s wherein the pixel analog circuit includes: an in-pixel feedback circuit keeping a voltage applied to the photoelectric conversion film at a constant level; and an in-pixel integrator circuit integrating and converting the photogenerated current into a voltage and a pixel initialization circuit initializing the integrator circuit (paragraph 0020 – 0021 biasing circuit 10 of the pixel circuit 101 or 103 includes an operational amplifier 20. The pixel circuit 101 illustrated in FIG. 1A or the pixel circuit 103 illustrated in FIG. 3, the photodiode PD and the operational amplifier 20 are arranged in a configuration commonly known as an integrator, in order to draw photo generated charges from the photodiode PD, thus keeping the voltage across the photodiode PD constant. Paragraph 0038 – 0039 operating the operational amplifier in a high power state with high bias current flowing through the internal circuit of the operational amplifier during a reset period or a readout period the photodiode so as to output an output signal and provide the constant bias voltage across the photodiode; accumulating the charges drained from the photodiode in a first charge-to-voltage converter (e.g., C1 in the pixel circuit 101 or the pixel circuit 103) and converting the accumulated charges into the corresponding output voltage during the image acquisition period. Resetting (e.g., the row control circuit 510 and/or SW2 in the pixel circuit 101 or the pixel circuit 103) the first charge-to-voltage converter during the reset period and prior to the image acquisition period such that the pixel analog biasing circuit 10 includes: an in-pixel feedback circuit, for operational amplifier 20 with capacitor C1, to keeping a voltage applied to the PD photoelectric conversion film at a constant level; and an in-pixel integrator of circuit operational amplifier 20 integrating and converting the PD photogenerated current into a voltage by a first charge-to-voltage converter and a pixel initialization switch SW2 in the pixel circuit 101 circuit initializing by reset the integrator circuit operational amplifier 20). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the circuitry of Hseih et al in a manner similar to Ganguly et al. Doing so would result improving Hseih et al invention in a similar way as Ganguly et al - namely the ability to provide an imager circuit with operational amplifier arrangement as an integrator that can be reset, in Ganguly et al invention, to the second layer analog circuit in the stacked imager circuit in Hseih et al invention.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hseih et al US Publication 2016/0165159 iv vie of Cremers US Publication 2020/0204750 as applied to claim 7 above, and further in view of Lee et al US Publication 2014/0146210.
Regarding claim 8 the combination of Hseih et al in view of Cremers teaches a stacked imager circuit with a second layer analog to digital circuit but do not expressively teach wherein a ramp waveform inputted to the pixel AD conversion circuit is adjusted for each shared pixel and changes a digital conversion gain;
Lee et al teaches an imager circuit with an ramping/ gain changing analog to digital circuit. Lee et al teaches of Fig. 1 – 12 of applicant’s wherein a ramp waveform inputted to the pixel AD conversion circuit is adjusted for each shared pixel and changes a digital conversion gain (paragraph 0042, Fig, 12, ramp signal generator 160 generates a ramp signal RS that is compensated for dark offset in response to a control signal CON. The ramp signal RS is applied to the CDS and ADC circuit 140 that performs A/D conversion. Paragraph 0057 the waveform of the ramp signal illustrated in the period D2 is generated for an ADC of the active pixel when a gain setting value of a comparator COM of FIG. 4 is 1X and the waveform of the ramp signal illustrated in the period D3 is generated for an ADC of the active pixel when a gain setting value of a comparator COM of FIG. 4 is 2X such that ramp signal generator 160 outputs a ramp waveform inputted to the pixel AD conversion circuit 140 is adjusted for each shared active pixel and changes a digital conversion gain from 1X to 2X as seen in Fig. 4). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the circuitry of Hseih et al in a manner similar to Lee et al. Doing so would result improving Hseih et al invention in a similar way as Lee et al - namely the ability to provide an imager circuit with an imager circuit with an ramping/ gain changing analog to digital circuit, in Lee et al invention, to the second layer analog to digital circuit in the stacked imager circuit in Hseih et al invention.
Allowable Subject Matter
Claims 4 – 6 are objected to as being dependent upon or ultimately dependent on a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARK T MONK whose telephone number is (571)270-7454. The examiner can normally be reached Monday thru Friday 8am to 4pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sinh Tran can be reached at 571-272-7564. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MARK T MONK/Primary Examiner, Art Unit 2637