DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/24/2026 has been entered.
Response to Amendment
The amendments filed 6/24/2026 have been accepted. Claims 1, 2, 5-11, 14-20, and 23-27 are still pending. Claims 1, 10, and 19 are amended. Applicant’s amendments to the claims have overcome each and every 103 rejection previously set forth in the Final Office Action mailed 4/16/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5, 10, 11, 14, 19, 20, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Ito (US PGPub 2008/0046649) in view of Jin (US PGPub 2019/0324690) in view of Bae (US PGPub 2021/0385298).
Regarding claim 1, Ito teaches a command responding method for a memory storage device, wherein the command responding method comprises: receiving an operation command from a host system (Fig. 5 and Paragraph [0049], states a write command can be received from the host), generating a response message according to the operation command, wherein the response message carries a first type response data and a second type response data (Fig. 5 and Paragraph [0051], states a write command receipt response can be sent to acknowledge the receipt of the write command (first data) can also contain a warning (second type response data)), the second type response data is not related to the execution result of the operation command (Fig. 5 and Paragraph [0051], the warning relates to whether the device is at an end of life stage), and the second type response data reflects a status of the memory storage device before receiving the operation command or generating the response message (Fig. 5 and Paragraphs [0046] and [0048], states the status can represent a warning as to whether or not the device is in an end of life state which it can reach before receiving the operation command. Fig. 5 and Paragraph [0051], show that the determination of status is done before writing the data), and sending the response message to the host system to respond to the operation command (Fig. 5 and Paragraph [0051], states the response is sent back to the host).
Ito also teaches, generating a response command according to an execution result of the operation command after executing the operation command, sending a response with first type response data reflects an execution result of the operation command (Paragraphs [0054] and [0056], states a write or read completion response can be sent once the operation completes which is done after the execution of the read or write operation). Since Ito teaches both sending a response with two types of data and after executing the operation command, sending a response with data related to the result of executing the operation it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute which command the warning (second response data) is sent with to obtain the predictable result of generating a response command according to an execution result of the operation command after executing the operation command, the operation command with first and second type response data, the first type response data reflects an execution result of the operation command (as all this does is change when the warning is sent and does not change the function or results of any of the other operations). Ito does not teach wherein the status comprises at least one of a temperature status and a working status, the temperature status reflects temperature of the memory storage device, and the working status reflects an execution status of an internal operation of the memory storage device, and wherein the response message further carries identification data to notify whether the response message carries the second type response data.
Jin teaches wherein the status comprises at least one of a temperature status and a working status, the temperature status reflects temperature of the memory storage device, and the working status reflects an execution status of an internal operation of the memory storage device (Paragraph [0079], states that the temperature status of the device can be monitored and sent to the host upon request). Since both Ito and Jin teach sending status information to the host it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the prior art elements according to known methods to modify the teachings of Ito to also send the temperature information as taught in Jin to obtain the predictable result of wherein the status comprises at least one of a temperature status and a working status, the temperature status reflects temperature of the memory storage device, and the working status reflects an execution status of an internal operation of the memory storage device. Ito and Jin do not teach wherein the response message further carries identification data to notify whether the response message carries the second type response data.
Bae teaches wherein the response message further carries identification data to notify whether the response message carries the second type response data (Paragraph [0089], states that the command can have bits that indicate whether or not the command includes reproduction data). Since both Ito/Jin and Bae teach sending commands with data it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the prior art elements according to known methods by modifying the teachings of Ito and Jin to also use bits to indicate the type of data as taught in Bae to obtain the predictable result of wherein the response message further carries identification data to notify whether the response message carries the second type response data.
Regarding claim 2, Ito, Jin, and Bae teach all the limitations to claim 1. Ito further teaches wherein the operation command comprises one of a writing command, a reading command, and an erasing command (Fig. 5 and Paragraph [0043], the command can be a write (used in the example), read, or a status read command). The combination of and reason for combining are the same as those given in claim 1.
Regarding claim 5, Ito, Jin, and Bae teach all the limitations to claim 1. Ito further teaches wherein the second type response data is stored in a reserved bit area in the response message (Paragraph [0051], the warning can be implemented as a bit in the reserve area of the response message). The combination of and reason for combining are the same as those given in claim 1.
Regarding claims 10, 11, and 14, claims 10, 11, and 14 are the device claims associated with claims 1, 2, and 5. Since Ito, Jin, and Bae teach all the limitations to claims 1, 2, and 5 and Ito further teaches a connection interface unit, configured to be coupled to a host system; a rewritable non-volatile memory module; and a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module (Fig. 1 and Paragraphs [0027]-[0028], show the memory device which includes pins (connection interface unit) to interface with the host, a card controller, and NAND memory), they also teach all the limitations to claims 10, 11, and 14; therefore the rejections to claims 1, 2, and 5 also apply to claims 10, 11, and 14.
Regarding claims 19, 20, and 23, claims 19, 20, and 23 are the control circuit claims associated with claims 1, 2, and 5. Since Ito, Jin, and Bae teach all the limitations to claims 1, 2, and 5 and Ito further teaches a memory control circuit unit, configured to control a memory storage device, wherein the memory storage device comprises a rewritable non-volatile memory module, and the memory control circuit unit comprises: a host interface, configured to be coupled to a host system; a memory interface, configured to be coupled to the rewritable non-volatile memory module; and a memory management circuit, coupled to the host interface and the memory interface (Fig. 1 and Paragraphs [0027]-[0028], show the memory device which includes pins (connection interface unit) to interface with the host, a card controller, and NAND memory. While it does not explicitly show the controller’s host and memory interfaces, since the controller needs to receive instructions from the host and send instructions to memory those interfaces have to exists), they also teach all the limitations to claims 19, 20, and 23; therefore the rejections to claims 1, 2, and 5 also apply to claims 19, 20, and 23.
Claims 6-8, 15-17, and 24-26 are rejected under 35 U.S.C. 103 as being unpatentable over Ito, Jin, and Bae as applied to claims 1, 10, and 19 above, and further in view of Lee et al. (US PGPub 2024/0220110, hereafter referred to as Lee).
Regarding claim 6, Ito, Jin, and Bae teach all the limitations to claim 1. Ito further teaches wherein generating the response message according to the execution result of the operation command after the operation command is executed comprises: detecting an event configured to generate the response message (Fig. 5 and Paragraph [0049], the write is meant to trigger a receipt and completion response), reading a status data in response to the event, wherein the status data reflects a status of the memory storage device (Fig. 5 and Paragraph [0070]-[0071], the status information used to determine whether or not the device is at end of life is read), and filling the second type response data into the response message according to the status data during a generation of the response message (Fig. 5 and Paragraph [0073], states the warning can be filled in the response if triggered). Ito, Jin, and Bae do not teach the use of a status register.
Lee teaches the use of a status register (Paragraphs [0054]-[055], states a status register can be used to store the health information for a storage device). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Ito, Jin, and Bae to use the status register of Lee so as to improved performance in the memory sub-system (Lee, Paragraph [0018]).
Regarding claim 7, Ito, Jin, Bae, and Lee teach all the limitations to claim 6. Ito further teaches writing the status data before detecting the event configured to generate the response message (Fig. 5 and Paragraph [0070]-[0071], as the status information is being read it means that it would have to have been written beforehand). Lee further teaches the use of status registers (Paragraphs [0054]-[055], as stated in the rejection to claim 6). The combination of and reason for combining are the same as those given in claim 6.
Regarding claim 8, Ito, Jin, Bae, and Lee teach all the limitations to claim 6. Ito further teaches writing the status data before receiving the operation command (Fig. 5 and Paragraph [0070]-[0071], as stated in the rejection to claim 7, the receiving of the command is the triggering event to generate the response messages). Lee further teaches the use of status registers (Paragraphs [0054]-[055], as stated in the rejection to claim 6). The combination of and reason for combining are the same as those given in claim 6.
Regarding claims 15-17, claims 15-17 are the device claims associated with claims 6-8. Since Ito, Jin, Bae, and Lee teach all the limitations to claims 6-8 and Ito further teaches a connection interface unit, configured to be coupled to a host system; a rewritable non-volatile memory module; and a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module (Fig. 1 and Paragraphs [0027]-[0028], show the memory device which includes pins (connection interface unit) to interface with the host, a card controller, and NAND memory), they also teach all the limitations to claims 15-17; therefore the rejections to claims 6-8 also apply to claims 15-17.
Regarding claims 24-26, claims 24-26 are the control circuit claims associated with claims 6-8. Since Ito, Jin, Bae, and Lee teach all the limitations to claims 6-8 and Ito further teaches a memory control circuit unit, configured to control a memory storage device, wherein the memory storage device comprises a rewritable non-volatile memory module, and the memory control circuit unit comprises: a host interface, configured to be coupled to a host system; a memory interface, configured to be coupled to the rewritable non-volatile memory module; and a memory management circuit, coupled to the host interface and the memory interface (Fig. 1 and Paragraphs [0027]-[0028], show the memory device which includes pins (connection interface unit) to interface with the host, a card controller, and NAND memory. While it does not explicitly show the controller’s host and memory interfaces, since the controller needs to receive instructions from the host and send instructions to memory those interfaces have to exists), they also teach all the limitations to claims 24-26; therefore the rejections to claims 6-8 also apply to claims 24-26.
Allowable Subject Matter
Claims 9, 18, and 27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims have been considered but are moot because the applicant amended the claims with the limitation “wherein the response message further carries identification data to notify whether the response message carries the second type response data” to overcome the prior rejections set forth in the Final Rejection mailed 4/16/2026. To address this, new reference Bae has been incorporated into the rejection to help teach the amended limitations.
Conclusion
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/NICHOLAS A. PAPERNO/Examiner, Art Unit 2132
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