DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-9 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim (US 2023/0207460 A1) .
The applied reference has a common inventor and assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claim 1, Kim discloses a semiconductor device (Figures 1, 3, 4, 6 and 13), comprising: a lower structure (Figure 13, reference 13); a first region (Figure 13, reference WLE2) including a plurality of first conductive layers (Figure 13, references 16A and 16B, left side) vertically stacked in a first direction over the lower structure (Figure 13, reference 13); a second region (Figure 13, reference WLE1) including a plurality of second conductive layers stacked in the first direction, the second conductive layers having the same horizontal length (Figure 13, references 16A and 16B, right side); and a plurality of contact structures (Figure 13, reference 22) coupled to the second conductive layers (Figure 13, references 16A and 16B, right side), respectively, wherein each of the second conductive layers (Figure 13, references 16A and 16B, right side) includes a first horizontal conductive line (Figure 13, reference 16A, right side); a second horizontal conductive line (Figure 13, reference 16B, right side); and a pad (Figure 13, reference 22) between the first horizontal conductive line (Figure 13, reference 16A, right side) and the second horizontal conductive line (Figure 13, reference 16B, right side).
Regarding claim 2, Kim discloses wherein the first horizontal conductive line (Figure 4, reference WE1), the second horizontal conductive line (Figure 4, reference WE2), and the pad (Figure 4, reference WLP1) have the same horizontal length (Figure 4, reference WLE1).
Regarding claim 3, Kim discloses wherein each of the first conductive layers (Figure 13, references 16A and 16B, left side) includes an upper horizontal conductive line extending from the WL2A first horizontal conductive line (Figure 13, reference 16B, left side); and a lower horizontal conductive line extending from the second horizontal conductive line (Figure 13, reference 16A left side).
Regarding claim 4, Kim discloses wherein each of the first conductive layers (Figure 13, references 16A and 16B, left side) includes: an upper horizontal conductive line extending from the first horizontal conductive line (Figure 13, reference 16B, left side); a lower horizontal conductive line extending from the second horizontal conductive line (Figure 13, reference 16A left side); and a horizontal layer (Figure 13, reference 22, left side) between the first horizontal conductive line (Figure 13, reference 16B, left side) and the second horizontal conductive line (Figure 13, reference 16A, left side).
Regarding claim 5, Kim discloses wherein each of the contact structures (Figure 6, reference WLP1-WLP4, equivalent to Figure 13, reference 22) includes: a plurality of contact plugs (Figure 6, references WC1-WC4) respectively coupled to the second conductive layers (Figure 6, references WL2A-WL2D); and contact spacers (Figure 6, reference ILD2) respectively disposed on sidewalls of the contact plugs (Figure 6, references WC1-WC4).
Regarding claim 6, Kim discloses wherein each of the contact structures (Figure 3, reference WLP1-WLP4, equivalent to Figure 13, reference 22) includes a plurality of contact plugs (Figure 3, references WC1-WC4) respectively coupled to the second conductive layers (Figure 3, references WLE1-WLE4), and the contact plugs (Figure 3, references WC1-WC4) have a structure whose height gradually decreases in a direction that the second conductive layers are stacked (Figure 3).
Regarding claim 7, Kim discloses wherein the contact structure (Figure 3, reference WLP1-WLP4, equivalent to Figure 13, reference 22) includes a deep contact plug (Figure 3, references WC1-WC4) coupled to a lowermost-level second conductive layer among the second conductive layers (Figure 3, references WLE1-WLE4), and the deep contact plug (Figure 3, references WC1-WC4) includes a shape that vertically penetrates the second conductive layers (Figure 3, references WLE1-WLE4).
Regarding claim 8, Kim discloses wherein the first conductive layers (Figure 13, reference 16A) and the second conductive layers (Figure 13, reference 16B) include the same material (paragraphs 0058-0060).
Regarding claim 9, Kim discloses a semiconductor device (Figure 3), comprising: a lower structure (Figure 3, reference SUB); a cell array region (Figure 3, reference MCA) including a plurality of horizontal conductive lines (Figure 3, references WLE1-WLE4) vertically stacked in the first direction over the lower structure (Figure 3, reference SUB); a connection region (Figure 3, reference BL) including a plurality of levels (Figure 3, reference ACT) stacked in the first direction and having the same horizontal length; and a plurality of contact structures (Figure 3, references WC1-WC4) respectively coupled to the levels (WLE1-WLE4), wherein each of the levels (Figure 3, reference ACT) includes a first horizontal conductive line (Figure 3, reference WL1); a second horizontal conductive line (Figure 3, reference WL2); and a pad (Figure 3, reference ACT) between the first horizontal conductive line (Figure 3, reference DWL4 upper) and the second horizontal conductive line (Figure 3, reference, DWL4 lower).
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ahn et al (US 2022/0157838 A1).
Regarding claim 10, Ahn et al discloses a semiconductor device (Figure 14B), comprising: an alternating stack (Figure 14B, reference 117)of conductive layers (Figure 14B, reference 122) and dielectric layers (Figure 14B, reference 118) disposed over a lower structure (Figure 14B, reference 1077); and an array of contact plugs (Figure 14B, reference 162) disposed in the alternating stack (Figure 14B, reference 117), horizontally spaced apart from each other in a first horizontal direction, and having different heights, wherein top surfaces of the contact plugs are disposed on the same horizontal plane (Figure 14B, reference 162), and bottom portions of the contact plugs (Figure 14B, reference 162) are coupled to the conductive layers (Figure 14B, reference 118), respectively, and wherein the contact plugs (Figure 14B, reference 162) penetrating an uppermost conductive layer (Figure 14B, reference 118) are laterally surrounded by the conductive layers (Figure 14B, reference 118) and are laterally surrounded by the conductive layers (Figure 14B, reference 118) laid over the conductive layers (Figure 14B, reference 118) adjoined with the contact structure (Figure 14B, reference 164g).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MONICA D HARRISON whose telephone number is (571)272-1959. The examiner can normally be reached M-F 7-4:30pm.
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/MONICA D HARRISON/Primary Examiner, Art Unit 2815
mdh
June 1, 2026
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