Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1-2, 8, 10, 17, and 19 are objected to because of the following informalities:
In line 11 of claim 1, “a bottom surface” should read “and a bottom surface”.
In line 3 of claim 2, “area” should be “areas”.
In line 3 of claim 8, “area” should be “areas”.
In lines 6 and 8 of claim 10, “integrated formed” should be “integrally formed”.
In line 3 of claim 17, “the same thickness” lacks explicit antecedent basis, but does not render the claim language indefinite. This should be corrected to read “a same thickness”.
In lines 6 and 10 of claim 19, “integrated formed” should be “integrally formed”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites “a fourth plug” without having first recited a second or third plug, “a third insulating layer” without having first recited a first or second insulating layer, and “a sixth conductive layer and a seventh conductive layer” without having first recited a third, fourth, or fifth conductive layer. It is unclear how there can be a fourth plug without there first being a second or third plug, a third insulating layer with there first being a first or second insulating layer, or a sixth or seventh conductive layer without there first being a third, fourth, or fifth conductive layer.
Claims 12-20 are dependent on claim 11, and therefore inherit the deficiencies of the parent claim. In addition, claims 16-20 are rejected due to the problems, separate from those of the parent claim, detailed below.
Claim 16 recites “a third plug” without having first recited a second plug, “a second insulating layer” without having first recited a first insulating layer, and “a fourth conductive layer and a fifth conductive layer” without having first recited a third conductive layer. It is unclear how there can be a third plug without there first being a second plug, a second insulating layer without there first being a first insulating layer or a fourth and a fifth conductive layer without there first being a third conductive layer.
Claims 17-20 are dependent on claim 16, and therefore inherit the deficiencies of the immediate parent claim.
For examination purposes, it will be assumed that:
The fourth plug recited in claim 11 is in fact a second plug.
The third insulating layer recited in claim 11 is in fact a first insulating layer.
The sixth and seventh conductive layers in claim 11 are in fact third and fourth conductive layers, respectively.
The fourth and fifth conductive layers of claim 16 are in fact fifth and sixth conductive layers, respectively.
To overcome these rejections, the applicant may:
Rename “a fourth plug” as recited in claim 11 and all of its dependent claims to “a second plug” or recite second and third plugs in claim 11.
Rename “a third insulating layer” as recited in claim 11 and all of its dependent claims to “a first insulating layer” or recite first and second insulating layers in claim 11.
Rename “a sixth conductive layer” and “a seventh conductive layer” as recited in claim 11 and all of its dependent claims to “a third conductive layer” and “a fourth conductive layer”, respectively, or recite third, fourth, and fifth conductive layers in claim 11.
Rename “a fourth conductive layer” and “a fifth conductive layer” as recited in claim 16 and all of its dependent claims to “a fifth conductive layer” and “a sixth conductive layer”, respectively, or recite a third conductive layer in either claim 11 or claim 16.
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Fig. 3 of Jang, reproduced with annotations added by the examiner.
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Fig. 5 of Jang, reproduced with annotations added by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Jang et. al., Pub. No. US 2022/0189966, hereafter referred to as Jang.
Regarding claim 1, Jang teaches all of the limitations of the claim in Figs. 3 and 5, reproduced above with annotations added by the examiner: “A semiconductor structure” ([0002]; Fig. 5), “comprising: a substrate” ([0040]; Fig. 5, substrate 100) “comprising a plurality of active areas” (Fig. 3; cell active regions ACT) “and a trench isolation” ([0038]; Fig. 5, cell region separation film 22); “and a plurality of plug structures” ([0052], [0073], [0080]; Fig. 5; storage contact 120 and storage pad 160, hereafter referred to as a storage contact structure, bit line structures 140ST, and dummy bit line structure 140ST_1) “and a plurality of spacers” ([0076]; Fig. 5, second and third cell line spacers 152 and 153) “alternately arranged on the substrate” (Fig. 5, note that the second and third cell line spacers 152 and 153 alternate with storage contact structures, bit line structures 140ST, and the dummy bit line structure 140ST_1), “the plurality of plug structures comprising a first plug disposed on one of the active areas” ([0052], [0073]; Fig. 5, note that the storage contact structure contacts one of the active areas) “and a second plug disposed on the trench isolation” ([0080]; Fig. 5, note that the dummy bit line structure 140ST_1 contacts the cell region separation film 22), “wherein the first plug comprises a first conductive layer” ([0073]; Fig. 5, storage contact 120; also see [0083]) “and a second conductive layer from bottom to top” ([0052]; Fig. 5, note that the storage pad 160 is above the storage contact 120; also see [0085]: “The storage pad 160 may include, for example, at least one of an impurity-doped semiconductor material such as doped polysilicon, a conductive silicide compound, a conductive metal nitride, a conductive metal carbide, a metal, and a metal alloy.”), “the second plug comprises a first insulating layer” ([0073]; Fig. 5, cell insulating film 130) “and a third conductive layer from bottom to top” ([0066]; Fig. 5, third cell conductive film 143; also see [0080]: “The dummy bit line structure 140ST_1 may have the same structure as the bit line structure 140ST, but may not be electrically active during operation of the semiconductor device.”), and “a bottom surface of the third conductive layer is lower than a bottom surface of the second conductive layer” (Fig. 5; note that the bottom surface of the third cell conductive film 143 in the dummy bit line structure 140ST_1 is below the bottom surface of the storage pad 160).
Regarding claim 2, Jang further teaches “The semiconductor structure according to claim 1, wherein the first conductive layer is in direct contact with the one of the active area”, (Fig. 5; note that the storage contact 120 is in contact with one of the active areas) “and the first insulating layer is in direct contact with the trench isolation” (Fig. 5; note that the cell insulating film 130 is in contact with the cell region separation film 22).
Regarding claim 3, Jang further teaches “The semiconductor structure according to claim 1, wherein the substrate further comprises a cell region” ([0040]; Fig. 3, cell region 20) “and a peripheral region” ([0038]; Fig. 3, peri region 24), “the active areas are disposed in the cell region” ([0040]; Fig. 3, cell active regions ACT), “and the trench isolation is disposed in the peripheral region” ([0038]; Fig. 3, cell region separation film 22; note that the cell region separation film may be considered part of the peripheral region).
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Fig. 2A of Kwon, reproduced with annotations added by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4-7 and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Jang in view of Kwon et. al., Pub. No. US 2024/0194597, hereafter referred to as Kwon.
Regarding claim 4, Jang teaches “The semiconductor structure according to claim 1, wherein the first conductive layer comprises a semiconductor material” (Jang [0083]: “The storage contact 120 may include, for example, at least one of an impurity-doped semiconductor material such as doped polysilicon…”), but does not teach “the second conductive layer and the third conductive layer comprise a same metal material.” However, Jang does teach that the second and third conductive layers may each be made of a metal (Jang [0085]: “The storage pad 160 may include, for example, …a metal”, [0067]: “The first to third cell conductive films 141, 142, and 143 may include, for example, …a metal”).
Kwon, on the other hand, teaches a contact plug (Kwon [0028]; Fig. 2A, reproduced above with annotations added by the examiner, contact plugs 162) and an upper conductive pattern (Kwon [0026]; Fig. 2A, upper conductive pattern 134B) that can both be made of tungsten (Kwon [0026]: “Each of the intermediate conductive pattern 132B and the upper conductive pattern 134B may include… W” and [0029]: “In an implementation, each of the plurality of contact plugs 162 may include… W”).
The materials of the contact plug and upper conductive pattern of Kwon can be incorporated into the device of Jang by making both the storage pad 160 and the third cell conductive film 143 out of tungsten. The combined device teaches “the second conductive layer and the third conductive layer comprise a same metal material” (Jang [0085]; Kwon [0026] and [0029]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have used tungsten, as taught by Kwon, as the metal material for the storage pad and third cell conductive film of Jang because tungsten is well known in the art to be a metal and it would have been a simple substitution of one material for another.
Regarding claim 5, the combined device of Jang and Kwon described in the discussion of claim 4 further teaches “The semiconductor structure according to claim 4, wherein the metal material comprises tungsten” (Kwon [0026] and [0029]), “and the semiconductor material comprises polycrystalline silicon” (Jang [0083]).
Regarding claim 6, Jang teaches “The semiconductor structure according to claim 1”, but does not teach “further comprising a metal silicide layer between the first conductive layer and the second conductive layer, wherein the bottom surface of the third conductive layer is lower than a bottom surface of the metal silicide layer.”
Kwon, on the other hand, does teach “further comprising a metal silicide layer between the first conductive layer and the second conductive layer” (Kwon [0029]; Fig. 2A, note that the metal silicide layer 158A is between the lower contact plug 156 and the contact plug 162).
The metal silicide layer of Kwon can be incorporated into the device of Jang by adding a metal silicide layer between the storage contact 120 and the storage pad 160. The combined device teaches “wherein the bottom surface of the third conductive layer is lower than a bottom surface of the metal silicide layer” (Jang Fig. 5; note that the metal silicide layer in the proposed combination can be made thin enough that its bottom surface is above that of the third cell conductive film 143).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have introduced a metal silicide layer, as taught by Kwon, between the storage contact and storage pad of Jang because such a layer can function as a diffusion barrier and it would be a simple combination of elements of the two disclosures.
Regarding claim 7, Jang teaches “The semiconductor structure according to claim 1”, but does not teach “further comprising an isolation sidewall between the third conductive layer of the second plug and one of the plurality of spacers, wherein the isolation sidewall and the first insulating layer form a U-shaped structure.” Jang, however, does show a cell insulating film 130 on the bottom of the dummy gate structure 140ST_1 and cell spacers 150 on one side of the dummy gate structure 140ST_1.
Kwon, on the other hand, teaches bit lines surrounded by an insulating layer (Kwon [0024]; Fig. 2A, second insulating layer 122B) and insulating spacers (Kwon [0027]; Fig. 2A, insulating spacers 152) that can each be made of an oxide or a nitride (Kwon [0024]: “Each of the first insulating layer 122A and the second insulating layer 122B may include an oxide layer, a nitride layer, or a combination thereof.”, [0027]: “The plurality of insulating spacers 152 may include an oxide layer, a nitride layer, an air spacer, or a combination thereof.”).
The insulating layer and insulating spacers of Kwon can be incorporated into the device of Jang as insulating layers surrounding the dummy bit line 140ST_1 and made out of the same oxide or nitride material. These may then all be treated as a single insulating layer, as they are all made from the same material. The combined device teaches “further comprising an isolation sidewall between the third conductive layer of the second plug and one of the plurality of spacers” (Kwon [0024] and [0027]), “wherein the isolation sidewall and the first insulating layer form a U-shaped structure” (Kwon Fig. 2A; note that a combination of the second insulating layer 122B and the insulating spacers 152 form a U-shaped structure).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have introduced insulating spacers, as taught by Kwon, into the device of Jang because such spacers would help to electrically isolate the dummy bit line from the other bit lines and contacts and it would be a simple combination of elements of the two disclosures.
Regarding claim 11, Jang teaches “A semiconductor structure” (Jang [0002]; Fig. 5), “comprising: a substrate” (Jang [0040]; Fig. 5, substrate 100) “comprising a cell region” (Jang [0040]; Fig. 3, cell region 20) “and a peripheral region” (Jang [0038]; Fig. 3, peri region 24), “the cell region comprising a plurality of active areas” (Jang [0040]; Fig. 3, cell active regions ACT), “and the peripheral region comprising a trench isolation” (Jang [0038]; Fig. 3, cell region separation film 22; note that the cell region separation film may be considered part of the peripheral region); “and a plurality of plug structures” (Jang [0052], [0073], [0080], and [0093]; Fig. 5; storage contact structure, bit line structures 140ST, dummy bit line structure 140ST_1, and block conductive structure 240ST_1) “and a plurality of spacers” (Jang [0076] and [0101-0102]; Fig. 5, second and third cell line spacers 152 and 153, etching stop film 250, and lower peri interlayer insulating film 290) “alternately arranged in the cell region and the peripheral region” (Jang Fig. 5; note that the plug structures each alternate with a spacer), “the plurality of plug structures comprising a first plug disposed on one of the active areas” (Jang [0052] and [0073]; Fig. 5, storage contact structure; note that the storage contact structure contacts an active area) “and a fourth plug disposed on the trench isolation” (Jang [0080]; Fig. 5, note that the dummy bit line structure 140ST_1 contacts the cell region separation film 22), “wherein the first plug comprises a first conductive layer” (Jang [0073]; Fig. 5, storage contact 120) “and a second conductive layer from bottom to top” (Jang [0052]; Fig. 5, note that the storage pad 160 is above the storage contact 120), “the fourth plug comprises a third insulating layer” (Jang [0073]; Fig. 5, cell insulating film 130), “a sixth conductive layer” (Jang [0066]; Fig. 5, first cell conductive film 141) “and a seventh conductive layer from bottom to top” (Jang [0066]; Fig. 5, third cell conductive film 143), and “the first conductive layer and the sixth conductive layer comprise a same semiconductor material” (Jang [0067]), but does not teach “and the second conductive layer and the seventh conductive layer comprise a same metal material.” Jang, however, does teach that the storage pad 160 and the third cell conductive film 143 may each be made out of a metal (Jang [0067] and [0085]).
Kwon, on the other hand, teaches a contact plug (Kwon [0028]; Fig. 2A, reproduced above with annotations added by the examiner, contact plugs 162) and an upper conductive pattern (Kwon [0026]; Fig. 2A, upper conductive pattern 134B) that can both be made of tungsten (Kwon [0026]: “Each of the intermediate conductive pattern 132B and the upper conductive pattern 134B may include… W” [0029]: “In an implementation, each of the plurality of contact plugs 162 may include… W”).
The materials of the contact plug and upper conductive pattern of Kwon can be incorporated into the device of Jang by making both the storage pad 160 and the third cell conductive film 143 out of tungsten. The combined device teaches “and the second conductive layer and the seventh conductive layer comprise a same metal material” (Jang [0085]; Kwon [0026] and [0029]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have used tungsten, as taught by Kwon, as the metal material for the storage pad and third cell conductive film of Jang because tungsten is well known to be a metal and it would have been a simple substitution of one material for another.
Regarding claim 12, the combination of Jang and Kwon described in the discussion of claim 11 further teaches “The semiconductor structure according to claim 11, wherein the first conductive layer is in direct contact with the one of the active areas”, (Fig. 5; note that the storage contact 120 is in contact with one of the active areas) “and the third insulating layer is in direct contact with the trench isolation” (Fig. 5; note that the cell insulating film 130 is in contact with the cell region separation film 22).
Regarding claim 13, the combined device of Jang and Kwon described in the discussion of claim 11 further teaches “The semiconductor structure according to claim 11, wherein the metal material comprises tungsten” (Kwon [0026] and [0029]), “and the semiconductor material comprises polycrystalline silicon” (Jang [0083]).
Regarding claim 14, the combined device of Jang and Kwon described in the discussion of claim 11 teaches “The semiconductor structure according to claim 11”, but does not teach “further comprising a metal silicide layer between the first conductive layer and the second conductive layer, and another metal silicide layer between the sixth conductive layer and the seventh conductive layer.” Jang, however, does teach a conductive silicide between the first and third cell conductive films 141 and 143 (Jang [0066]; Fig. 5, second cell conductive film 142; also see [0067]: “The first to third cell conductive films 141, 142, and 143 may include, for example, … a conductive silicide compound”).
Kwon, on the other hand, does teach “further comprising a metal silicide layer between the first conductive layer and the second conductive layer” (Kwon [0029]; Fig. 2A, note that the metal silicide layer 158A is between the lower contact plug 156 and the contact plug 162) “and another metal silicide layer between the sixth conductive layer and the seventh conductive layer” (Kwon [0025]; Fig. 2A, intermediate conductive pattern 132B; also see [0026]: “Each of the intermediate conductive pattern 132B and the upper conductive pattern 134B may include… tungsten silicide”).
The metal silicide layer of Kwon can be incorporated into the device of Jang by adding a metal silicide layer between the storage contact 120 and the storage pad 160 and making the second cell conductive film 142 a metal silicide.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have introduced a metal silicide layers, as taught by Kwon, between the storage contact and storage pad of Jang and to make the second cell conductive film of Jang a metal silicide because such layers can function as diffusion barriers and it would be a simple combination of elements of the two disclosures.
Regarding claim 15, Jang teaches “The semiconductor structure according to claim 11, further comprising an isolation sidewall between the first conductive layer of the first plug and one of the plurality of spacers” (Jang [0078]; note that the first and fourth cell line spacers 151 and 154 contact both the storage contact 120 and the second and third cell line spacers 152 and 153), but does not teach “another isolation sidewall between the seventh conductive layer of the fourth plug and the one of the plurality of spacers.” Jang, however, does show a cell insulating film 130 on the bottom of the dummy gate structure 140ST_1 and cell spacers 150 on one side of the dummy gate structure 140ST_1.
Kwon, on the other hand, teaches bit lines surrounded by an insulating layer (Kwon [0024]; Fig. 2A, second insulating layer 122B) and insulating spacers (Kwon [0027]; Fig. 2A, insulating spacers 152) that can each be made of an oxide or a nitride (Kwon [0024] and [0027]).
The insulating layer and insulating spacers of Kwon can be incorporated into the device of Jang as insulating layers surrounding the dummy bit line 140ST_1. The combined device teaches “another isolation sidewall between the seventh conductive layer of the fourth plug and the one of the plurality of spacers” (Kwon [0024] and [0027]; note that the insulating layers so introduced would contact the spacers in the combined device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have introduced insulating spacers, as taught by Kwon, into the device of Jang because such spacers would help to electrically isolate the dummy bit line from the other bit lines and contacts and it would be a simple combination of elements of the two disclosures.
Allowable Subject Matter
Claims 8-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 16-20 would be allowable if rewritten to overcome the rejections under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The references of record, whether considered individually or in combination, do not teach or suggest the limitations of:
Claim 8, which teaches “wherein the plurality of plug structures further comprise a third plug, which crosses a junction between another one of the active area and the trench isolation and comprises a second insulating layer, a fourth conductive layer and a fifth conductive layer from bottom to top, wherein the first conductive layer and the fourth conductive layer comprise a same semiconductor material, and the second conductive layer, the third conductive layer and the fifth conductive layer comprise a same metal material.”
Claim 9 is dependent on claim 8, and therefore contains the same allowable subject matter.
Claim 10, which teaches “an extension pad disposed on the second plug and integrated formed with the third conductive layer.”
Claim 16, which teaches “wherein the plurality of plug structures further comprise a third plug, which crosses a junction between another one of the active areas and the trench isolation and comprises a second insulating layer, a fourth conductive layer and a fifth conductive layer from bottom to top, wherein the fourth conductive layer comprises the semiconductor material, and the fifth conductive layer comprise the metal material.”
Claims 17-20 are dependent on claim 16, and therefore contain the same allowable subject matter.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT EMIL THROCKMORTON whose telephone number is (571) 272-. The examiner can normally be reached 7:30 AM - 12 PM and 1 PM - 5:30 PM ET Monday-Thursday, 7:30 AM - 11:30 AM and 12:30 PM - 4:30 PM ET Friday.
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/R.E.T./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
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